Cirrus Logic Inc.

Tony J Yoon

Joe Chen

John S Geldman

Christopher P Zook

Phuc Tran

Keisuke Kato

Michael J McGrath

Frederick Siu-Huang Au

An efficient error correction processor is disclosed for correcting a multi-dimensional code comprising a first set of codewords that intersect with a second set of codewords. The error correction is carried out by performing iterative passes over the first and second set of codewords. The individual codewords are corrected using error syndromes which are computed as a function of the codeword data. In the preferred embodiment, the individual codewords are encoded according to a Reed-Solomon code and the error syndromes are computed as the modulo division of the codeword polynomial by the factors of a generator polynomial. To increase the throughput of the error correction processor, a syndrome buffer is employed to facilitate generating the error syndromes for both the first and second set codewords concurrently. In this manner, after a pass over the first set of codewords, the error syndromes for the second set codewords are available for immediate processing. In one embodiment, the syndrome buffer stores the error syndromes for both the first and second set codewords so that only one pass over the codewords is necessary to generate the error syndromes. In subsequent passes, the error syndromes are available immediately; they are not regenerated as in the prior art.

Concurrent row/column syndrome generator for a product code

The invented controller is the combination of: an intelligent interface to a SCSI bus, a multi-port buffer memory manager, a formatter, and a local processor port. With the addition of a few components for the device-level interface, the invented controller along with a buffer RAM, a local processor system, and an optional data separator completes a high performance disk, or other mass storage, controller subsystem. The invention is particularly directed to (1) the dual use of a buffer memory as data buffer storage and for storage of instructions to be executed by a SCSI-protocol processor, (2) the architecture of the interface to the SCSI bus, and (3) the instruction set of the SCSI-protocol processor.

Flexible processor-driven SCSI controller with buffer memory and local

The invented controller is the combination of: an intelligent interface to a SCSI bus, a multi-part buffer memory manager, a formatter, and a local processor port. With the addition of a few components for the device-level interface, the invented controller along with a buffer RAM, a local processor system, and an optional data separator completes a high performance disk, or other mass storage, controller subsystem. The invention is particularly directed to (1) the dual use of a buffer memory as data buffer storage and for storage of instructions to be executed by a SCSI-protocol processor, (2) the architecture of the interface to the SCSI bus, and (3) the instruction set of the SCSI-protocol processor.

Flexible processor-driven control of SCSI buses utilizing tags appended

A subcode R-W channel data de-interleaving and de-scrambling method and apparatus includes the ability to de-interleave and de-scramble the encoded subchannel data without the necessity of storage elements, by dynamically calculating the final location of each byte of data within a packet as it is read from the CD-Rom. A pack counter monitors the pack number of the current byte of data. An index counter monitors the location of the current data within a pack. A subtractor uses the values from the pack counter and the index counter to obtain an input value, a first portion of which is supplied to a first offset generator. A second portion of the subtractor output is used to select a base address. The first offset generator determines the pack number of the current byte of data after the de-interleave process. A second offset generator receives a value from the index counter and generates a corresponding value. The results from the first offset generator and the second offset generator are both input into a first adder. The output of the first adder is added to the selected base address by a second adder in order to calculate the final address. The final address is transmitted with the current byte of data to an external buffer memory, where it is stored in the specified address. Preferably the present invention is included in a dedicated integrated circuit which calculates the final address of each byte of subchannel R-W data as it is read.

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San Jose, CA, United States of America

Tony J Yoon