Bay Microsystems, Inc.

Hitachi Micro Systems, Inc.

Tony J Chiang

Man Dieu Trinh

Simon S Chong

Goichiro Ono

Charles F Gershman

Barry T Lee

Jun-Wen Tsong

Steve C Chen

Eric K Yang

Ryzsard Bleszynski

Richard W Blasco

Basant Khaitan

Tahir Sheikh

A network processor for processing information elements is described. Each information element is associated with a flow and comprises at least one information element segment. A policy controller stores an information element into at least one information segment storage unit within a memory, and determines whether an information element segment conforms to a predetermined quality of service ('QoS'). A traffic processor selects the information element segment for forwarding based on at least one QoS parameter. A forwarding processor forwards the selected information element segment to an egress port.

Network processor architecture

A memory buffer for buffering data from an external memory to a processor including a cache memory, a first-in-first-out memory, a direct data path, a writing selector for writing data from the external memory to one of the cache memory, first-in-first-out memory and direct data path, a reading selector for reading data from one of the cache memory, first-in-first-out memory and direct data path and a controller for controlling the writing and reading selectors in response to the occurrence of certain conditions.

Instruction cache buffer with program-flow control

Growing community of inventors

Fremont, CA, United States of America

Tony J Chiang