Via Technologies, Inc.

Test-rite Products Corporation

Tony Ho

Judy Lee

Chung-Ching Huang

Norman Chung

Wayne Tseng

Ting-Hsien Wang

Bob Cheng

Bouryi Sze

A combined car jack and lug wrench assembly is provided that includes a driving lever configured to be used both to engage a driving head for operating a hydraulic system of the car jack and to be used as a spanner of a lug wrench assembly. The assembly can include a car jack body, a socket storage assembly disposed on the body for housing wrench sockets, and a lever storage assembly disposed on a sidewall of the body configured to secure the driving lever along a sidewall of the body, when not in use.

Combined car jack and lug wrench assembly

A trash can assembly is provided having an outer shell and a lid pivotally coupled to the shell for movement between an open position and a closed position. A foot pedal is operatively coupled to the lid such that pressing down on the pedal caused the lid to open. A fluid damper is mounted to dampen the downward movement of a lid. The damper engages a support surface operatively coupled to the lid such that the support surface moves in conjunction with movement of the lid as the lid moves between the open position and the closed position, and yet the fluid damper is unsecured to the support surface.

Trash can assembly

An electrostatic discharge protection circuit has a substrate; a first P-well installed on the substrate and having a first P+-doped region and a first N+-doped region, both of which are connected to ground; a second P-well installed on the substrate and having a second P+-doped region and a second N+-doped region, both of which are connected to a power supply voltage; and a third P-well installed on the substrate and having a third N+-doped region, a third P+-doped region, and a fourth N+-doped region, all of which are for input/output signals.

Electrostatic discharge protection circuit

Cosmetic station

Ergonomic wrench

In a power management method of a computer system, the CPU asserts a clock-suspending grant cycle in response to a clock-suspending signal issued by the south bridge chip, and the south bridge chip issues the clock-suspending signal in response to a data write cycle asserted by the CPU. The clock-suspending grant cycle is to be transmitted to the south bridge chip via the north bridge chip when the CPU is ready to enter a power-saving mode. The north bridge chip performs a first power management operation of the peripheral device in response to the clock-suspending grant cycle. The south bridge chip performs a second power management operation of the computer system in response to the clock-suspending grant cycle.

Power-state management of peripheral device by north bridge for power management of computer system

An interruption control system includes an interruption message generator, a stop clock control module and an interruption status indicating path. The interruption message generator is used for decoding and identifying a message signaled interrupt (MSI) issued by a first peripheral device or a second peripheral device when interruption is to be conducted, and generates an interruption status indicating message in response to the message signaled interrupt (MSI). The stop clock control module is coupled to the interruption message generator and the CPU and de-asserts a stop clock signal that is previously asserted to have the CPU enter a power-saving state to have the CPU deactivate the power-saving state in response to the interruption status indicating message. The interruption status indicating path is used for transmitting the interruption status indicating message.

Interruption control system and method

An interruption control system includes a PIC, an APIC and a power management unit disposed in a south bridge chip of a computer system. In response to the triggering of an interrupt status indicating signal received through an interrupt status indicating pin of a north bridge module or by the triggering of a peripheral device coupled to the south bridge chip, the PIC sends an interrupt signal to the CPU via an interrupt request signal pin when the computer system is in a PIC mode. The APIC is disabled when the computer system is in the PIC mode, and enabled when the computer system is in an APIC mode to generate a memory write cycle message to the CPU in response to the triggering of the peripheral device. The power management unit is optionally triggered with the interrupt signal or the interrupt status indicating signal to awake the CPU.

Interruption control system

An interruption control system includes a first input/output interruption controller, a second input/output interruption controller, and an interruption control device bus. The first input/output interruption controller is coupled to a first peripheral device and a south bridge chip, and asserts a wake-up signal to the south bridge chip in response to a first interrupt signal issued by the first peripheral device so as to deactivate a power-saving state of the computer system. The second input/output interruption controller is coupled to a second peripheral device and a north bridge chip, and asserts a third interrupt signal in response to a second interrupt signal issued by the second peripheral device. Via the interruption control device bus, the third interrupt signal is transmitted from the second input/output interruption controller to the first input/output interruption controller, wherein the first input/output interruption controller asserts the wake-up signal to deactivate the power-saving state of the computer system in response to the third interrupt signal.

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Taipei, Taiwan

Tony Ho