Divio, Inc.

Cirrus Logic Inc.

Tony H Wu

Ren-Yuh Wang

James C Chan

Sandy Lee

Fong-Jim Wang

A method and apparatus for concatenating data words from a bitstream includes a scratch memory ( ) containing last words of unfinished blocks and left-aligned extra data words of finished blocks. A previous register ( ) holds one last word of an unfinished block. A next register ( ) holds a first of possibly many extra data words associated with the last word. A bit detector ( ), coupled to the previous register ( ) and the next register ( ), first concatenates the last word and the first extra data word and identifies selected bits for the detection of a valid code word. When no more valid code words can be found from the selected bits, and more data associated with the unfinished block exists, the first extra data word is moved to the previous register ( ) and a second extra data word is moved to the next register ( ). The first extra data word and the second extra data word are concatenated for the detection of another valid code word. In various embodiments of the present invention, a start bit register ( ) and a remaining bits register ( ) hold values that are used in concatenation and the detection of valid code words.

Method and apparatus for concatenating bits of odd-length words

New and improved methods and apparatus for run-length encoding video data. These techniques are especially suited to digital video applications, in which input to a video decoder is generated in order to determine run lengths and amplitudes. The implementations are suitable for widely-used image compression standards that integrate various algorithms into a compression system, such as the standards specified in the Digital Video Standard (the &ldquo;Blue Book&rdquo;).

Method and apparatus for run-length encoding video data

New and improved methods and apparatus for concatenating data words from a bitstream. These techniques are especially suited to digital video applications, in which input to a video decoder is generated in order to determine run lengths and amplitudes. This implementation is suitable for widely-used image compression standards that integrate various algorithms into a compression system, such as the standards specified in the Digital Video Standard (the &ldquo;Blue Book&rdquo;).

A phase comparator compares phase of a clock signal and a generated comparison clock signal based upon rising edges. The output of the phase comparator may include a series of short up (U) pulses or down (D) pulses, depending whether the phase of the comparison clock is leading or lagging the clock. Up and down pulses U and D control an up/down shift register which in turn compensates phase difference by inserting or removing additional discrete delay elements in a variable delay line. Based upon delay signals generated by the variable delay line, a double frequency clock generator generates a 2.times. clock signal. The 2.times. clock signal is divided by 2 in a divider to supply the phase comparator with the generated comparison clock signal. The feedback scheme helps the digital delay lock loop of stabilize after a few clock cycles without additional external control. The use of digital delay elements in the delay lock loop eliminates the need for large analog circuits used in PLLs, and thus saves silicon (wafer) space. In addition, the digital circuitry of the present invention consumes less power than a comparable analog PLL. Moreover, the circuit of the present invention will lock at phase quickly. The digital design of the present invention may also be less sensitive to technology type (i.e., types of digital design) and thus be transitioned to future designs with less debugging and the like.

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Milpitas, CA, United States of America

Tony H Wu