Infineon Technologies Ag

Austriamicrosystems Ag

Tony Gschier

Bernd Zimek

Thomas Santa

George Efthivoulidis

Peter Thurner

A radar monolithic microwave integrated circuit (MMIC) includes a trigger encoder configured to receive a clock signal comprising a plurality of clock pulses having a fixed amplitude and a trigger signal configured to indicate trigger events. The trigger encoder is configured to encode the trigger signal into the clock signal to generate a distributed clock signal by skipping at least one clock pulse of the plurality of clock pulses to indicate a trigger event. The radar MMIC is configured to output the distributed clock signal having the at least one clock pulse skipped to indicate the trigger event. The radar MMIC is configured to receive the distributed clock signal as a received distributed clock signal. The radar MMIC further includes a radar operation controller configured to detect the trigger event based on the received distributed clock signal and initiate a radar operation based on detecting the trigger event.

Trigger signaling through a clock signal in cascading radar systems

A circuit arrangement for generating an IQ signal which comprises an oscillator () and a frequency divider (). The oscillator () and the frequency divider () are arranged in a common current path between the supply and reference potentials () in accordance with the proposed principle. It is possible to operate the two function blocks using a common BIAS current and additionally to save components.

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Graz, Austria

Tony Gschier