Intel Corporation

Tony G Hamilton

Leonard O Turner

Roger Sakuma

Marty Goodman

A method is described that involves storing active sleep mode software instructions to be executed by a low end central processing unit into an on chip cache that caches normal active mode software instructions executed by a high end central processing unit. The active sleep mode software instructions are to be executed by the low end central processing unit during an active sleep mode. The normal active mode software instructions are executed by the high end central processing unit during a normal active mode. The active sleep mode consumes less power than the normal active mode.

Method and apparatus for a computing system having an active sleep mode CPU that uses the cache of a normal active mode CPU

A method is described that involves storing active sleep mode software instructions to be executed by a low end central processing unit into an on chip cache of a high end central processing unit that caches normal active mode software instructions executed by the high end central processing unit. The active sleep mode software instructions are to be executed by the low end central processing unit during an active sleep mode. The normal active mode software instructions are executed by the high end central processing unit during a normal active mode. The active sleep mode consumes less power than the normal active mode.

An apparatus a first processor which receives a data transfer request and generates a service command that corresponds to a scalable logic block required to respond to the data transfer request, and a server computer that receives the service command and scales the scalable logic block in accordance with the service command.

Computing device with scalable logic block to respond to data transfer requests

An apparatus is described. The apparatus includes a computing system having a normal active mode and an active sleep mode. The active sleep mode consumes less power than the normal active mode. The computing system also has a high end system and a low end system. The low end system executes one or more tasks during the active sleep mode.

Method and apparatus for a computing system having an active sleep mode

A method and apparatus to detect a power change in a system (e.g. computer) and to automatically adjust, in response to the power change, the performance states (e.g. supply voltages, clock frequencies and buffer strengths) of a plurality of system components (e.g. buses). The apparatus includes a detector and a controller.

Power management by transmitting single multiplexed signal to multiple system components to change settings of internal performance registers in response to change in power source

A shielded socket includes a conducting plate including a plurality of apertures, and an insulating layer. The insulating layer surrounds the conducting plate and lines at least one aperture. In an implementation, the conducting plate includes at least one grounding site.

Method of fabricating a shielded zero insertion force socket

Shielded zero insertion force socket

Included in the system are a memory module, a controller, and a voltage regulator. The memory module stores data indicating a level of voltage needed for operation. The controller obtains the data from the memory module and outputs a signal, based on the data, indicating the level of voltage needed by the memory module. The voltage regulator receives the signal from the controller, and supplies the level of voltage to the memory module in accordance with the signal.

Growing community of inventors

Durham, NC, United States of America

Tony G Hamilton