International Business Machines Corporation

Lenovo (singapore) Pte. Ltd.

Tony Emile Sawan

Diyanesh B Chinnakkonda Vidyapoornachary

Prasanna Jayaraman

Marc Avery Gollub

Robert Walter Berry, Jr

Ray Clement Laning

Saurabh Chadha

Anand Haridass

Brad William Michael

Vijay Anand Mathiyalagan

Maureen Terese Davis

Diyanesh B Chinnakkonda

Diyanesh Babu Vidyapoornachary Chinnakkonda

Eakambaram Rangaswamy Thirumalai

Adam Samuel Hale

Justin Ginn

Warren Edward Maule

Sundeep Chadha

James K Wong

Khajistha Fattu

Sean Dalton

Michael Fattu

Brandon Lackey

Ryan Bergsma

Katherine Ann Dunning

Ricardo Escobar

Sudhi Ranjan Proch

Madhav Peri

Charles Paul Hofer

Rocio Yolanda Garza

Eakambaram R Thirumalai

Embodiments herein describe a memory controller that has an encryption path and a bypass path. Using an indicator (e.g., a dedicated address range), an outside entity can inform the memory controller whether to use the encryption path or the bypass path. For example, using the encryption path when performing a write request means the memory controller encrypts the data before it was stored, while using the bypass path means the data is written into memory without be encrypted. Similarly, using the encryption path when performing a read request means the controller decrypts the data before it is delivered to the requesting entity, while using the bypass path means the data is delivered without being decrypted.

Encrypting data using an encryption path and a bypass path

Memory based encryption using an encryption key based on a physical address

Critical path failure analysis using hardware instruction injection may include providing, by an instruction microcontroller, to a plurality of processor cores, one or more test instruction sequences, wherein the instruction microcontroller is coupled to, for each of the plurality of processor cores: a first multiplexor providing an input to an instruction queue, and a second multiplexer receiving an input from the instruction queue and providing an output to an execution pathway; performing, by the instruction microcontroller, based on one or more test instruction sequences, one or more of a scan-in last pass (SLP) analysis or a scan-in cycle offset (SCO) analysis; and determining, based on one or more of the SLP analysis or the SCO analysis, one or more of a critical instruction sequence or a critical component path associated with the plurality of processor cores.

Critical path failure analysis using hardware instruction injection

Hardware acceleration using a self-programmable coprocessor architecture may include determining that an instruction cache comprises an accelerable instruction sequence; instead of executing the accelerable instruction sequence, providing, to an accelerator block of an accelerator complex comprising a plurality of accelerator blocks, a complex instruction corresponding to the accelerable instruction sequence, wherein the accelerator block comprises one or more reprogrammable logic elements configured to execute the complex instruction; and receiving, from the accelerator complex, a result of the complex instruction.

Hardware acceleration using a self-programmable coprocessor architecture

An apparatus for core repair includes a failure analysis and recovery ('FAR') probe that accesses a core of a processor and units of the core over a low-level communication bus while the core is operational after a failure notification. The FAR probe compares operational data of the core versus vital product data ('VPD') while the core is running tests and a thermal, power, functional (&#x201c;TPF&#x201d;) workload to determine if the core is in a degraded state and runs tests to identify a failure after determining that the core is in a degraded state. The FAR probe adjusts parameters of the core in response to identifying a failure of the core and re-evaluates the core to determine if the core is functional. The FAR probe returns the core to service after determining that the core is functional. The FAR probe operates independent of other processor cores while the cores are operational.

Core repair with failure analysis and recovery probe

Managing network communications is provided. An indication that a network device has been added to a local network is received. In response to receiving the indication that the network device been added to the local network, metrics corresponding to the network device added to the local network are detected. A device fingerprint corresponding to the network device added to the local network is generated based on the detected metrics.

Device aware network communication management

A method, apparatus, system, and computer program product for displaying information. A display system comprises a display device with pixels, a lenticular lens system, a sensor system, and a controller. The lenticular lens system is located on the pixels in the display device. The sensor system is positioned to detect a position of eyes of an authorized user with respect to the display device. The controller determines an authorized viewing angle of each lenticular lens to the eyes of the authorized user in the lenticular lens system using the position of the eyes of the authorized user and turns on a set of the pixels such that the authorized user sees information at the authorized viewing angle.

Managing information display of a display system

An apparatus for cognitive data center management is disclosed. A computer-implemented method and computer program product also perform the functions of the apparatus. According to an embodiment of the present invention, the apparatus includes a performance module that determines performance metrics over a predetermined time interval at a device coordinate in a three-dimensional ('3D') coordinate system for each replaceable device of a plurality of replaceable devices within a data center. The apparatus maps the performance metrics to environmental sensor measurements taken in the 3D coordinate system. The apparatus further includes an input analysis module that uses discovery analytics to determine a predicted time to failure for each replaceable device. The apparatus further includes a preventative action module that determines recommended actions to prevent failure of the replaceable devices and a tradeoff learning module that provides updated weighting factors based on changes to performance metrics in response to taking recommended actions.

Cognitive data center management

An aspect includes a method for dynamic random access memory (DRAM) scrub and error counting. A scrub operation is performed at memory locations in a DRAM. The performing includes, for each of the memory locations: receiving a refresh command at the DRAM; executing a read/modify/write (RMW) operation at the memory location, the executing including writing corrected bits to the memory location; and incrementing an error count in response to detecting an error during the executing. The method also includes comparing the error count to an error threshold. An alert is initiated in response to the error count exceeding the error threshold.

Autonomous dram scrub and error counting

It is determined that a guard band frequency for a first processor is to be determined. The guard band frequency is associated with a first system configuration. A validation start frequency is determined based, at least in part, on data associated with at least one of the first processor or a second processor. The validation start frequency is between a nominal operating frequency for the first processor and a system maximum operating frequency for the first processor. A guard band frequency for the second processor was previously determined. The guard band frequency for the first processor is determined based, at least in part, on the validation start frequency.

Frequency guard band validation of processors

Methods, apparatuses, and products for budgeting for power consumption in a chassis environment that includes a plurality of integrated technology elements ('ITEs'), each ITE having power utilization information indicating an average power consumption of the ITE, including: determining, by a chassis management module, a total power requirement value based on a sum of the average power consumption for each ITE; increasing, by the chassis management module, the total power requirement value in dependence upon a predetermined power utilization delta; identifying, by the chassis management module, one or more power supplies to provide power to the ITEs in the chassis environment in dependence upon power delivery capabilities of the one or more power supplies and the total power requirement value; and powering on the identified one or more power supplies by the chassis management module.

Budgeting for power consumption in a chassis environment that includes a plurality of integrated technology elements

Mirrored memory scrubbing is optimized to reduce system power consumption and increase system performance. A memory scrub operation scrubs a first portion of the mirrored memory to detect and correc soft errors. The scrub rate of a second portion of the mirrored memory is eliminated, minimized, or reduced, relative to the scrub rate of the first portion. The reduced scrub operation preserves power consumed in association with scrubbing the second portion.

Memory scrubbing in a mirrored memory system to reduce system power consumption

Mirrored memory scrubbing is optimized to reduce system power consumption and increase system performance. A memory scrub operation scrubs a first portion of the mirrored memory to detect and correct soft errors. The scrub rate of a second portion of the mirrored memory is eliminated, minimized, or reduced, relative to the scrub rate of the first portion. The reduced scrub operation preserves power consumed in association with scrubbing the second portion.

An aspect includes a method for receiving a memory allocation request for a logical partition. Partition mirroring is enabled for the logical partition. Unscrubbed memory is allocated to both a first and a second copy of the logical partition, with the second copy of the logical partition mirroring the first copy of the logical partition. Scrubbing of the first and second copy of the logical partitions is initiated. Subsequent to initiating the scrubbing one of the first and second copy of the logical partition is selected and partition mirroring is disabled for the logical partition. The first copy of the logical partition is deallocated based on selecting the second copy of the logical partition. The second copy of the logical partition is deallocated based on selecting the first copy of the logical partition.

Memory system power management

An aspect includes memory error recovery in a memory system includes detecting an error condition within a memory chip of the memory system. A chip mark is applied to the memory chip to flag the error condition. An address range of the memory chip associated with the error condition is determined. Data are written from the address range of the memory chip to a cache memory. The chip mark is removed based on determining that all of the data from the address range have been written to the cache memory.

Growing community of inventors

Round Rock, TX, United States of America

Tony Emile Sawan