Advanced Micro Devices Corporation

Legerity, Inc.

Tony E Sawan

Sharif Mohammad Sazzad

Jagannathan Bharath

Philip Chu Yip

Muhammad M Rahmatullah

A memory-efficient system and method for generating data blocks &ldquo;on demand&rdquo; for TDMA data bursts. In one embodiment of the present invention, a GSM transmitter module converts forward error correction (FEC) coded full-rate speech frames into TDMA data blocks. The transmitter module includes a memory configured to store the FEC coded frames in a current frame buffer and a previous frame buffer, an address generator configured to generate addresses of words in the current frame buffer during even clock cycles and addresses of words in the previous frame buffer during odd clock cycles. To generate the word addresses, the address generator operates on word offsets provided by a bit position generator, which also generates intra-word bit offsets. The memory provides the data words requested by the address generator to a multiplexer, which the selects a bit from each of the data words as indicated by the intra-word bit offsets from the bit position generator. The stream of bits from the multiplexer forms the bit reordered and frame interleaved data for the data blocks.

System and method for bit interleaving of full-rate speech data

A digital signal processor (DSP), hardware module, and shared memory coupled together to perform Viterbi decoding on a sequence of received symbols. Given channel coefficients, the DSP calculates initial data for Viterbi processing: combination values for each possible state and branch product values for each possible symbol. These values are stored in shared memory for access by the hardware module. The DSP further calculates the first few stages of the Viterbi processing so path metrics are well defined for every state. Path metric values are also stored into the shared memory. The hardware module is optimized to perform calculations associated with a single stage of the Viterbi algorithm. The DSP invokes by the hardware module by passing a received sample to the hardware module. The hardware module calculates a survivor state value and minimizing path metric value for each state in the state space.

MLSE implementation using a general purpose DSP and shared hardware for a GSM application

A memory-efficient system and method for generating data blocks 'on demand' for TDMA data bursts. In one embodiment of the present invention, a GSM transmitter module converts forward error correction (FEC) coded full-rate speech frames into TDMA data blocks. The transmitter module includes a memory configured to store the FEC coded frames in a current frame buffer and a previous frame buffer, an address generator configured to generate addresses of words in the current frame buffer during even clock cycles and addresses of words in the previous frame buffer during odd clock cycles. To generate the word addresses, the address generator operates on word offsets provided by a bit position generator, which also generates intra-word bit offsets. The memory provides the data words requested by the address generator to a multiplexer, which the selects a bit from each of the data words as indicated by the intra-word bit offsets from the bit position generator. The stream of bits from the multiplexer forms the bit reordered and frame interleaved data for the data blocks.

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Austin, TX, United States of America

Tony E Sawan