International Business Machines Corporation

Tony E Parker

Timothy V Lee

Joseph K Farrell

Jeffrey S Gordon

Daniel C Kuhl

Robert V Jenness

Gerard A Veneski

Victor S Moore

Wayne R Kraft

William L Stahl, Jr

Joseph C Rhodes, Jr

A computer system that is able to specify a packet size transmission rate is disclosed. The computer system has a plurality of nodes, each node being serially connected on a P1394 bus to at least one other node in the computer system. The nodes communicate one to another by transmitting communication packets having variable byte sizes over the P1394 bus. The packet size transmission rate is specified by first establishing an average transmission of bytes per packet. Next, the system determines an approximate value of the average transmission rate and, based on this value, determines a periodic change on the average transmission rate for transmitting communication packets of length l or length l+1. Once the periodic change is understood, the system selects a repeating pattern for generating a sequence of packets representing this approximate value. This sequence allows for an even transmission distribution of l and l+1 packets. The system bases its selection on checking the repeating pattern to determine whether the transmission rate should change from l to l+1 or vice versa and changing the transmission rate upon indication that a change is necessary.

Method and system for matching packet size for efficient transmission

Disclosed is an arrangement for 'seamlessly' integrating telephone services relative to primitive analog telephone equipment into general purpose computer systems. The integration is effected through present 'secondary' adaptation of data link control adapter devices which are adapted primarily for coupling such computer systems to high speed data communication links for transmission and reception of digital data. This permits general resources of the computer system (keyboard, memory, disk drives, etc.) to be used for specific applications associated with telephone services. Presently described link control devices have a telephone attachment port which couples through analog-to-digital conversion circuits to a primitive analog telephone (no dial or keys). Such devices operate normally in time division multiplex to process communication data between a computer (host) system and data link ports. The present adaptation includes a host programmable time division switch circuit within the control device, which can be conditioned dynamically to route digitized telephone signals directly between its data link and telephone ports, whereby telephone signals can be transmitted isochronally between a local user of the host system and a remote telephone, over a telephone network connection, while data signals are being transferred in either direction between the host system and equipment at the remote telephone station over the same connection.

Adapter for interfacing a computer to a multichannel digital network,

Subject burst time division multiplex interface connects circuits which perform 'layer 1 (L1)' line control functions relative to a data communication network with devices which perform 'Layer 2 (L2)' link control functions relative to the same network (L1 and L2 defined by OSI Specifications of the International Standards Organization). The interface is characterized by presentation of bursts of readiness indicating pulses from the L1 circuit to the L2 device during each basic time division multiplex time slot. The pulses indicate readiness of the circuits for data bit exchange, and separate time overlapped bursts are sent to indicate readiness of the circuits to send and receive data bits. Each burst contains a varied number of pulses ranging from 0 to n (where n is greater than 2, and in the disclosed embodiment equals 8). The bursts are positioned in a window of time occupying a fraction of the slot interval close to the end of each slot. This allows the L2 device to perform state swapping operations during the remainder of the slot to prepare for burst exchanges with different network channels to which the slots are allocatable and to be able to devote maximum processing time to performance of L2 tasks required relative to the channels. The channels operate under various communication protocols; e.g. High-Level Data Link Control (HDLC), Link Access Procedure-D (LAP-D), clear voice, etc. Slot time spacings are variable by the L1 circuits to adjust to signalling conditions in the network.

Burst time division multiplex interface for integrated data link

An integrated data link control device (IDLC) interfaces between a host computer system and external channels in a communication network. The device contains multiple internal channels allocatable individually to interface to the external channels, each internal channel having internal buffer memory reserved to it for storing data signals handled by it. The device also includes facilities for selectively configuring groups of its internal channels into 'extended channels', some of which are termed Hyper Channels. Channels in each extended channel group interface collectively and in time coordination to one external channel, presenting an effective bandwidth to the external channel which is greater than the bandwidth of any single internal channel. One channel in each group is designated as a reference channel for the group, and all data signals transferred between the group and the assigned external channel are funneled through only the buffer memory assigned to the respective reference channel; in order to ensure that such signals are transferred between the external channel and the host system in their correct 'message' sequence.

Data link controller with channels selectively allocatable to hyper

A single chip integrated data link control (IDLC) device provides full duplex data throughput and versatile protocol adaptation between variably configured time channels on a high speed TDM digital link (e.g. T-1 or T-3 line) and a host data processing system. The device can handle multiple channels of voice and varied protocol data traffic, and thereby is suited for use in primary rate ISDN (Integrated Services Digital Network) applications. Synchronous and asynchronous special purpose logic sections in the device respectively interface with the network and a bus extending to external processing systems. Logic in the synchronous section forms plural-stage receive and transmit processing pipelines relative to the network interface. A 'resource manager' element (RSM) and time swap (TS) RAM memory operate to dynamically vary states in these pipelines in synchronism with channel time slots at the network interface, whereby each pipeline operates in multitasking mode to perform plural functions relative to each channel during each time slot. The device also includes integrated memory queues in which communication data and channel status information are stacked relative to the device interfaces. Capacities and modes of operation of these queues are selected to minimize effects on chip size, throughput and cost, while supporting operations in the synchronous section pipelines so that critical time dependencies between consecutive pipeline stages, and between the pipelines and external processors, are lessened.

Integrated data link controller with synchronous link interface and

A microword control system is provided for producing the sequences of microwords used to control the execution of processor instructions in a microprogrammed digital data processor. This microword control system includes a plurality of programmable logic array mechanisms responsive to the processor instruction to be executed for individually producing different ones of the microwords needed to execute such instruction. This microword control system also includes microword-responsive control circuitry for controlling the operation of the data processor. This microword control system further includes multiplexing circuitry for supplying microwords from different ones of the programmable logic array mechanisms to the control circuitry during different time intervals.

Microword control system utilizing multiplexed programmable logic arrays

A microcode control mechanism is provided for producing the sequences of microwords used to control the execution of processor instructions in a microprogrammed data processor. This microcode control mechanism includes sequence counter circuitry for supplying a sequence of numbers and a programmable logic array mechanism responsive to the processor instruction and to the sequence of numbers for producing a sequence of microwords needed to execute the instruction. The microcode control mechanism also includes repeat circuitry responsive to a predetermined microword produced by the programmable logic array mechanism for setting the sequence counter circuitry back to a count which is less than the current count for causing a selected portion of the microword sequence to be repeated. The microcode control mechanism further includes a programmable repeat counter for counting the number of times the selected portion is repeated and for disabling the repeating action after a selected number of repeats.

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Boca Raton, FL, United States of America

Tony E Parker