Eon Silicon Solution Inc.

Tony Chan

Takao Akaogi

A method of identifying a damaged bitline address in a non-volatile memory device is introduced. The non-volatile memory device includes a memory cell array and a plurality of bit lines crossing the memory cell array. Each bit line has a first end and a second end. The bit lines are divided into a first group and a second group. The method includes applying a source voltage (charging) or ground voltage (discharging) to a specific group of bit lines, testing the bit lines in two testing stages (open-circuit testing and short-circuit testing) by the principle that no damaged bit line can be charged or discharged, and acquiring an address data of a damaged bit line according to a status data stored in a page buffering circuit and related to whether a bit line is damaged, thereby dispensing with a calculation process for estimating the address of the damaged bit line.

Method of identifying damaged bitline address in non-volatile

A semiconductor device and a method for accelerating erase verification process thereof are introduced, in which a correction unit of erase verification is connected between broken bit lines of the semiconductor device and a page buffer. Grounding switches in the correction unit of erase verification are allowed to connect the broken bit lines to ground during an erase verification process by means of a specific circuit arrangement with respect to the broken lines. Thereby, the earth voltage is received, and further, that the broken bit lines pass the erase verification is identified by the page buffer, further saving time consumed in repeated verifications in the conventional technology significantly.

Semiconductor device for accelerating erase verification process and method therefor

A method of testing bitlines in a non-volatile memory device is introduced. The non-volatile memory device includes a memory cell array and a plurality of bitlines crossing the memory cell array. Each of the bitlines has a first end and a second end. The bitlines are divided into a first group and a second group. The testing method includes applying a supply voltage (for charging) or a ground voltage (for discharging) to a specific group of bitlines. The bitlines are tested in two testing stages, namely an open-circuit bitline test and a short-circuit bitline test, based on the feature that a defective bitline cannot be charged or discharged. The open-circuit bitline test and the short-circuit bitline test are quick and dispense with a lengthy programmed/erasing process.

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Chu-Pei, Taiwan

Tony Chan