Nec Corporation

Tonomi Egawa

Kazuyuki Yamasaki

The provision of a semiconductor memory device for which access times in burst mode can be improved with no increase in the chip surface area and with no increase in power consumption. A latch pulse selection circuit uses a control signal CA T to output an input control signal SALF and a control signal SALS, to a first latch group within a latch circuit as a latch pulse SAL A, and to a second latch group within the latch circuit as a latch pulse SAL A, respectively. Based on a control signal YS &tilde;YS input from a column decoder circuit , a Y selector is connected to a sense amplifier circuit via Y switches connected to the corresponding digit lines. The sense amplifier circuit comprises sense amplifiers, and performs data evaluations of the signal YD &tilde;signal YD from the Y selector. A latch circuit latches a data signal DT &tilde;data signal DT from the sense amplifier circuit into a first latch group and a second latch group via latch signals SAL and SAL respectively.

Semiconductor memory device and method for reading data

The data to be saved by the ECC are grouped into lower digit data and higher digit data as outputs of a binary circuit, and by saving in the ECC circuit in the first established data input sequence, it is possible to save by the ECC in every lower and higher digit data delivered before reading out all data, so that the saving process time is shortened.

Multi-value type semiconductor memory device and its defect removal method

A semiconductor memory device in accordance with this invention having multi-valued memory cell that stores a plurality of bits has a recognition apparatus judging whether an input address signal designates upper data or designates lower data among a plurality of bits, a row selecting apparatus selecting word lines corresponding with the input address signal and applying to selected word lines only word line voltages necessary for reading out upper data or lower data among a plurality levels of word line voltages corresponding with results of the recognition apparatus, a column selecting apparatus selecting bit lines in accordance with the input address signal, and an output apparatus generating output data in accordance with levels of the selected bit lines.

Growing community of inventors

Kanagawa, Japan

Tonomi Egawa