Intel Corporation

Tonia G Morris

Jonathan C Jasper

Arnaud J Forestier

John V Lovelace

Kevin M Connolly

Saravanan Sethuraman

Christopher P Mozak

Christopher E Cox

David G Ellis

John R Goles

Yu Ying Ong

Siaw Kang Lai

Christina Jue

Zhenglong Wu

Benjamin T Tyson

Yee Choong Lim

Bill Nale

Uttam K Sengupta

Kannan Raj

Cynthia S Bell

Nikhil M Deshpande

Ying Zhou

Phillip E Mattison

James E Breisch

Jean-Charles Korta

Ramesh Subashchandrabose

Lohit R Yerva

Daniel Becerra Perez

Lawrence D Blankenbeckler

Daniel Becerra

Larry A Booth, Jr

Moshe Jacob Finkelstein

Alberto David Perez Guevara

Cyrus M Afghahi

Michael J Fink

A reference voltage value and a chip select (CS) signal timing delay provided to memory devices can be determined based on samples of the CS signal received by the memory devices. The CS signal can be provided to the memory devices with varying time delays and for various reference voltages. Various samples of the CS signal from the memory devices can indicate different times for rising and falling edges of the CS signal. A composite signal eye can be generated by the latest occurring rising edge and the earliest occurring falling edge of the CS signal. The reference voltage value and timing delay can be chosen based on the composite signal eye width that is the closest to a reference eye width.

Training for chip select signal read operations by memory devices

An integrated circuit may include circuitry for accessing an associated die stack. The circuitry may receive temperature information as well as a plurality of operating parameters that help determine whether it may be desirable to reroute access commands or requests to one or more die in the stack. The circuitry may include a smart crossbar switch that implements an address translation or hashing function to help map the logical user address to a physical address space. Performing thermally aware traffic management in this way can ensure that acceptable timing margins are maintained in the system to minimize the probability of errors.

Methods and apparatus for managing thermal behavior in multichip packages

Techniques and mechanisms for providing communications which facilitate link training. In an embodiment, a memory controller includes, or couples to, trainer circuitry which is configured to provide instructions to generate memory access commands. The instructions are accessed at the circuitry in response to an indication that link training is performed, where the accessing is independent of communication with a processor coupled to the memory controller. Based on the instructions, memory access commands are communicated via a link between the memory controller and a memory device. Link training is performed based on an evaluation of one or more characteristics of the link communications. In another embodiment, memory access commands are generated, based on the instructions, while a validity of data at the memory device is maintained.

Device, system and method to generate link training signals

A method is described. The method includes receiving from a memory controller configuration information for a testing sequence and storing the configuration information in configuration register space of the driver circuit. The method also includes controlling the next testing sequence. The testing sequence includes sweeping values of a tap coefficient of a DFE circuit of the driver circuit and sweeping a voltage of a slicer of the driver circuit. The method includes sending results of the testing sequence to the memory controller. The results are to determine a value for the DFE tap coefficient.

Registering clock driver controlled decision feedback equalizer training process

A chip select training mode (CSTM) enables a memory subsystem to train a chip select signal separately from command bus training. A memory device and a memory controller can connect via a command bus including a chip select signal line. Instead of training the chip select along with other signal lines of the command bus, a CSTM mode enables the memory subsystem to more accurately train the chip select. The memory device can be triggered for CSTM mode with a command, and then train voltage margining for the CS signal line to align chip select signaling with the memory subsystem clock signal.

Efficiently training memory device chip select control

A memory subsystem enables per device addressability (PDA) to target configuration commands to one of multiple memory devices that share a select line or buffer devices that share an enable line. The system includes a host and multiple memory devices that can be coupled over a command bus and a data bus. The devices include a configuration or mode register to store a value to indicate whether PDA enumeration is enabled. When enabled, the host can provide an enumeration identifier (ID) command via the command bus with a signal via the data bus to assign an enumeration ID. After assignment of the enumeration ID, the host can send PDA commands via the command bus with the enumeration ID, without a signal on the data bus. Devices only process PDA commands that match their assigned enumeration ID, enabling the setting of device-specific configuration settings without needing to use the data bus on every PDA command.

Enumerated per device addressability for memory subsystems

A method performed by a memory chip is described. The method includes receiving an activated chip select signal. The method also includes receiving, with the chip select signal being activated, a command code on a command/address (CA) bus that identifies a next portion of an identifier for the memory chip. The method also includes receiving the next portion of the identifier on a portion of the memory chip's data inputs. The method also includes repeating the receiving of the activated chip select signal, the command code and the next portion until the entire identifier has been received and storing the entire identifier in a register.

Memory bus MR register programming process

A host controller apparatus for determining information related to a time shift for transmitting instructions on a command and address bus includes an interface for transmitting a plurality of instruction signals to a memory module via the command and address bus and for receiving a loopback feedback signal from the memory module. The host controller apparatus further includes a control module configured to transmit the plurality of instruction signals to the memory module via the command and address bus. The control module is configured to receive the loopback feedback signal from the memory module. The loopback feedback signal includes a looped-back composite version of the plurality of instruction signals. The control module is configured to determine the information related to the time shift for transmitting instructions on the command and address bus based on the loopback feedback signal.

Host controller apparatus, host controller device, and method for a host controller for determining information related to a time shift for transmitting instructions on a command and address bus, host controller and computer system

Provided are a device and computer readable storage medium for programming a memory module to initiate a training mode in which the memory module transmits continuous bit patterns on a side band lane of the bus interface; receiving the bit patterns over the bus interface; determining from the received bit patterns a transition of values in the bit pattern to determine a data eye between the determined transitions of the values; and determining a setting to control a phase interpolator to generate interpolated signals used to sample data within the determined data eye.

Read training a memory controller

Embodiments are generally directed to signal phase optimization in memory interface training. An embodiment of an apparatus includes an interface for at least one signal; and interface training logic capable of automatically adjusting a phase relationship between the signal and a strobe or clock, including establishing a phase delay of the signal and a phase delay of the strobe or clock for training of the interface, wherein the interface training logic is capable of determining a phase delay reduction for the signal subsequent to measurement of an eye margin for the signal, the phase delay reduction to retain a sufficient delay to maintain the eye margin for sampling of the signal.

Signal phase optimization in memory interface training

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Irmo, SC, United States of America

Tonia G Morris