Intel Corporation

Toni Juan

Roger Espasa

Jesus Corbal

Joel S Emer

Federico Ardanaz

Roger Gramunt

Geoff Lowney

Santiago Galan

Isaac Hernandez

Edward Thomas Grochowski

Ravi Rajwar

Eric A Sprangle

Andrew Thomas Forsyth

Joshua B Fryman

Ramacharan Sundararaman

John Cruz Mejia

In one embodiment, the present invention includes an apparatus having a register file to store vector data, an address generator coupled to the register file to generate addresses for a vector memory operation, and a controller to generate an output slice from one or more slices each including multiple addresses, where the output slice includes addresses each corresponding to a separately addressable portion of a memory. Other embodiments are described and claimed.

Implementing vector memory operations

In one embodiment, a method includes receiving an instruction for decoding in a processor core and dynamically handling the instruction with one of multiple behaviors based on whether contention is predicted. If no contention is predicted, the instruction is executed in the core, and if contention is predicted data associated with the instruction is marshaled and sent to a selected remote agent for execution. Other embodiments are described and claimed.

Adaptively handling remote atomic execution based upon contention prediction

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Barcelona, Spain

Toni Juan