Huawei Technologies Co., Limited

Tonglong Zhang

Xiaodong Zhang

Yong Guan

Heng Li

Simin Wang

A chip package on package structure includes a primary chip stack unit having pins insulated and spaced from each other on a first surface; a first bonding layer disposed on the first surface, where the first bonding layer includes bonding components insulated and spaced from each other, each bonding component includes a bonding part, and any two bonding parts are insulated and have a same cross-sectional area, and the bonding components are separately bonded to the pins; and secondary chip stack units, disposed on a surface of a side that is of the first bonding layer and that is away from the primary chip stack unit, where the secondary chip stack unit has micro bumps insulated and spaced from each other, and each of the micro bumps is bonded to one of the bonding components.

Chip package on package structure, packaging method thereof, and electronic device

A chip package structure includes a first chip, a second chip, and a carrier board. The first chip is disposed between the second chip and the carrier board. An active layer of the first chip is opposite to an active layer of the second chip. A first interconnection structure is disposed between the first chip and the second chip and is configured to couple the active layer of the first chip to the active layer of the second chip. A first conductor pillar is disposed in the first chip. One end of the first conductor pillar is coupled to the active layer of the first chip, and the other end of the first conductor passes through the first chip to be coupled to a circuit in the carrier board.

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Shenzhen, China

Tonglong Zhang