Future Wei Technologies, Inc.

Tong Sun

Weizhong Chen

Yuanbin Guo

Alan Gatherer

Lee Dobson McFearin

Peter Yan

Zhikun Cheng

Fang Yu

Bin Yang

Ashish Rai Shrivastava

Debashis Bhattacharya

Sushma Wokhlu

Mark W Brown

Zhihong Li

Alex Elisa Chandra

Ywhpyng Harn

Xiaotao Chen

Xingfeng Chen

Yan Bei

Ke Ning

Chushun Huang

Technology for providing data to a processing unit is disclosed. A computer processor may be divided into a master processing unit and consumer processing units. The master processing unit at least partially decodes a machine instruction and determines whether data is needed to execute the machine instruction. The master processing unit sends a request to memory for the data. The request may indicate that the data is to be sent from the memory to a consumer processing unit. The data sent by the memory in response to the request may be stored in local read storage that is close to the consumer processing unit for fast access. The master processing unit may also provide the machine instruction to the consumer processing unit. The consumer processing unit may access the data from the local read storage and execute the machine instruction based on the accessed data.

Main processor prefetching operands for coprocessor operations

An embodiment of a system and method for performing a numerical operation on input data in a hybrid floating-point format includes representing input data as a sign bit, exponent bits, and mantissa bits. The exponent bits are represented as an unsigned integer including an exponent bias, and a signed numerical value of zero is represented as a first reserved combination of the mantissa bits and the exponent bits. Each of all other combinations of the mantissa bits and the exponent bits represents a real finite non-zero number. The mantissa bits are operated on with a 'one' bit before a radix point for the all other combinations of the mantissa bits and the exponent bits.

System and method for a floating-point format for digital signal processors

Methods and apparatus for inter-process communication are provided. A circuit may have a plurality of clusters, and at least one cluster may have a computation element (CE), a memory operatively coupled with the CE, and an autonomic transport system (ATS) block operatively coupled with the CE and the memory. The ATS block may be configured to perform inter-process communication (IPC) for the at least one cluster. In one embodiment, the ATS block may transfer a message to a different cluster based on a request from the CE. In another embodiment, the ATS block may receive a message by allocating a buffer in the memory and write the message into the buffer. The ATS block may also be configured to manage synchronization and schedule tasks for the CE.

Scalable autonomic message-transport with synchronization

An apparatus and method are provided for allocating resources to a plurality of threads to perform a service. In use, a request for service is received. At least one of a plurality of resources is allocated to the threads. Further, the service is performed with the threads, utilizing the allocated at least one resource.

Apparatus and method for allocating resources to threads to perform a service

An embodiment of a method and a related apparatus for digital computation of a floating point complex multiply-add is provided. The method includes receiving an input addend, a first product, and a second product. The input addend, the first product and the second product each respectively has a mantissa and an exponent. The method includes shifting the mantissas of the two with smaller exponents of the input addend, the first product, and the second product to align together with the mantissa of the one with largest exponent of the input addend, the first product and the second product, and adding the aligned input addend, the aligned first product and the aligned second product.

System and method for signal processing in digital signal processors

According to one embodiment, an apparatus includes a digital signal processor configured to perform a multiple antenna detection portion of a baseband signal processing process using a first floating point processing unit, and perform all other portions of the baseband signal processing process using a half-precision floating point processing unit. The first floating point processing unit has a bit width that is larger than the bit width of the half-precision floating point processing unit.

Efficient baseband signal processing system and method

An embodiment of an apparatus performs a floating-point multiply-add process on a first multiplicand, a second multiplicand, and an addend. A leading 0 bit is added to a mantissa of the first multiplicand to form an expanded first mantissa, and a partial-product multiplication is performed on the expanded first mantissa and a mantissa of the second multiplicand to produce partial-product sum and a partial-product carry mantissas. Leading bits of the partial-product sum and carry mantissas are changed to 0 bits if they are both 1 bits, and the partial-product sum and the partial-product carry are shifted right according to an exponent difference of a product of the first multiplicand and the second multiplicand. Otherwise both the partial-product sum and carry mantissas are arithmetically shifted right according to the exponent difference. The first and second multiplicands and the addend can be complex numbers.

Systems and methods for a floating-point multiplication and accumulation unit using a partial-product multiplier in digital signal processors

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Allen, TX, United States of America

Tong Sun