Chartered Semiconductor Manufacturing Ltd (corporation)

International Business Machines Corporation

Samsung Electronics Co., Ltd.

Globalfoundries Singapore Pte. Ltd.

Tong Qing Chen

Liang Choo Hsia

Fan Zhang

Pradeep Yelehanka

Bei Chao Zhang

Kelvin Ong

Tian Hao Gu

Syn Kean Cheah

Zhi Yong Han

Juan Boon Tan

Jia Zhen Zheng

Chim Seng Seet

Yi-Hsiung Lin

Bo Tao

Yong Chiang Ee

John Leonard Sudijono

Johnny Widodo

Wan-jae Park

Yong Kong Siew

Jae Hak Kim

Wan Jae Park

Zhen Jia Zheng

San Leong Liew

Hyung-yoon Choi

An integrated circuit is provided. A gate dielectric and a gate are provided respectively on and over a semiconductor substrate. A junction is formed adjacent the gate dielectric and a shaped spacer is formed around the gate. A spacer is formed under the shaped spacer and a liner is formed under the spacer. A first dielectric layer is formed over the semiconductor substrate, the shaped spacer, the spacer, the liner, and the gate. A second dielectric layer is formed over the first dielectric layer. A local interconnect opening is formed in the second dielectric layer down to the first dielectric layer. The local interconnect opening in the first dielectric layer is opened to expose the junction in the semiconductor substrate and the first gate. The local interconnect openings in the first and second dielectric layers are filled with a conductive material.

Semiconductor local interconnect and contact

A method for forming a semiconductor device is presented. The method includes providing a substrate prepared with a dielectric layer formed thereon. The dielectric layer having a conductive line disposed in an upper portion of the dielectric layer. The substrate is processed to produce a top surface of the dielectric layer that is not coplanar with a top surface of the conductive line to form a stepped topography.

Reliable interconnects

Method of Fabricating Interconnections of a Microelectronic Device Using a Dual Damascene Process. A method of fabricating interconnections of a microelectronic device includes preparing a semiconductor substrate comprising a lower dielectric layer and a lower interconnection, forming an etch stopper layer and an interlayer dielectric layer on the semiconductor substrate, forming a via hole in the interlayer dielectric layer so that the etch stopper layer is exposed through the via hole, performing carbon doping on the etch stopper layer, performing trench etching to form a trench in the interlayer dielectric layer so that the trench overlaps part of the via hole, removing the carbon-doped etch stopper layer, and filling the via hole and the trench with a conductive material to form an upper interconnection.

Method of fabricating interconnections of microelectronic device using dual damascene process

A method of forming a barrier layer and cap comprised of CuSiN for an interconnect. We provide an interconnect opening in a dielectric layer over a semiconductor structure. We form a CuSiN barrier layer over the sidewalls and bottom of the interconnect opening by reacting with the first copper layer. We then form an interconnect over the CuSiN layer filling the interconnect opening. We can form a CuSiN cap layer on the top surface of the interconnect.

Entire encapsulation of Cu interconnects using self-aligned CuSiN film

Methods of forming electrical interconnect structures include forming a dielectric layer on a semiconductor substrate and forming a hard mask layer on the dielectric layer. A photoresist layer is patterned on an upper surface of the hard mask layer. This patterned photoresist layer is used as an etching mask during a step to selectively etch the hard mask layer and define an opening therein. This opening exposes the first dielectric layer. The patterned photoresist layer is then stripped from the hard mask layer using an ashing process that exposes the upper surface of the hard mask layer. Following this ashing process, a portion of the first dielectric layer extending opposite the opening is selectively etched using the hard mask layer as an etching mask. During this selective etching step, polymer residues are accumulated directly on the upper surface of the hard mask layer. These polymer residues may operate to increase a degree of selectively and inhibit recession of the hard mask layer during the step of selectively etching the first dielectric layer.

Methods of forming electrical interconnect structures using polymer residues to increase etching selectivity through dielectric layers

An integrated circuit, and manufacturing method therefor, is provided. A gate dielectric and a gate are provided respectively on and over a semiconductor substrate. A junction is formed adjacent the gate dielectric and a shaped spacer is formed around the gate. A spacer is formed under the shaped spacer and a liner is formed under the spacer. A first dielectric layer is formed over the semiconductor substrate, the shaped spacer, the spacer, the liner, and the gate. A second dielectric layer is formed over the first dielectric layer. A local interconnect opening is formed in the second dielectric layer down to the first dielectric layer. The local interconnect opening in the first dielectric layer is opened to expose the junction in the semiconductor substrate and the first gate. The local interconnect openings in the first and second dielectric layers are filled with a conductive material.

Method of manufacturing semiconductor local interconnect and contact

Growing community of inventors

Singapore, Singapore

Tong Qing Chen