Taiwan Semiconductor Manufacturing Comp. Ltd.

Tong-Chern Ong

Wen-Ting Chu

Yu-Wen Liao

Ming-Tsong Wang

Harry-Hak-Lay Chuang

Hung Cho Wang

Sheng-Huang Huang

Kuei-Hung Shen

Kuo-Yuan Tu

Kuo-Chi Tu

Ying-Lang Wang

Kuo-Ching Huang

Sheng-Hung Shih

Chun-Yang Tsai

Jen-Sheng Yang

Shih-Lien Linus Lu

Yu-Der Chih

Fu-Lung Hsueh

Chung-Cheng Chou

Jun-De Jin

Ya-Chen Kao

Chun-Jung Lin

Sa-Lly Liu

Ping-Lin Yang

Albert Chin

Jian-Hsing Lee

Shou-Gwo Wuu

Kuo-Feng Yu

Kuo-Yu Chou

Ming-Hsiang Song

Shao-Chang Huang

Chun-Yao Ko

Yi-Hsun Wu

Chung-Wei Chang

Han-Chi Liu

Chin-Shan Hou

Shu-Chuan Lee

Hsueh-Jen Yang

Chun-Hung Lai

Chung-Jung Lee

Jui-Ling Yang

Jun-Yi Wu

The present disclosure relates to an integrated circuit. The integrated circuit includes a an inter-layer dielectric (ILD) structure laterally surrounding a conductive interconnect. A dielectric protection layer is disposed over the ILD structure and a passivation layer is disposed over the dielectric protection layer. The passivation layer includes a protrusion extending outward from an upper surface of the passivation layer. A bottom electrode continuously extends from over the passivation layer to between sidewalls of the passivation layer. A data storage element is over the bottom electrode and a top electrode is over the data storage element.

Memory device

The present disclosure, in some embodiments, relates to a method of forming a resistive random access memory (RRAM) device. The method includes forming one or more bottom electrode films over a lower interconnect layer within a lower inter-level dielectric layer. A data storage film having a variable resistance is formed above the one or more bottom electrode films. A lower top electrode film including a metal is over the data storage film, one or more oxygen barrier films are over the lower top electrode film, and an upper top electrode film including a metal nitride is formed over the one or more oxygen barrier films. The one or more oxygen barrier films include one or more of a metal oxide film and a metal oxynitride film. The upper top electrode film is formed to be completely confined over a top surface of the one or more oxygen barrier films.

Electrode structure to improve RRAM performance

The present disclosure, in some embodiments, relates to a resistive random access memory (RRAM) device. The RRAM device includes a bottom electrode that is disposed over a lower interconnect layer surrounded by a lower inter-level dielectric (ILD) layer. A data storage structure is arranged over the bottom electrode and a multi-layer top electrode is disposed over the data storage structure. The multi-layer top electrode includes conductive top electrode layers separated by an oxygen barrier structure that is configured to mitigate movement of oxygen between the conductive top electrode layers. A sidewall spacer is disposed directly over the bottom electrode and has a sidewall that covers outermost sidewalls of the conductive top electrode layers and the oxygen barrier structure.

A semiconductor device includes a memory circuit and a logic circuit. The memory circuit includes a word line, a bit line, a common line and a memory transistor having a gate coupled to the word line, a drain coupled to the bit line and a source coupled to the common line. The logic circuit includes a field effect transistor (FET) having a gate, a drain and a source. The memory transistor has a gate electrode layer formed on a gate dielectric layer, and the gate dielectric layer includes a first insulating layer and a first ferroelectric (FE) material layer. The FET has a gate electrode layer formed on a gate dielectric layer, and the gate dielectric layer includes a second insulating layer and a second FE material layer.

Semiconductor device and manufacturing method thereof

A circuit includes a memory array having a plurality of memory cells; a control logic circuit, coupled to the memory array, and configured to use a first voltage signal to cause a first memory cell of the plurality of memory cells to transition from a first resistance state to a second resistance state; a counter circuit, coupled to the control logic circuit, and configured to increment a count by one in response to the first memory cell's transition from the first to the second resistance state; and an encryption circuit, coupled to the counter circuit, configured to generate an encrypted value using an updated count provided by the counter circuit.

RRAM-based monotonic counter

The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a control device arranged within a substrate and having a terminal. A first memory device is coupled between the terminal of the control device and a first bit-line. A second memory device is coupled between the terminal of the control device and a second bit-line.

Memory circuit and formation method thereof

The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method may include forming a control device within a substrate. A first plurality of interconnect layers are formed within a first inter-level dielectric (ILD) structure over the substrate. A first memory device and a second memory device are formed over the first ILD structure. A second plurality of interconnect layers are formed within a second ILD structure over the first ILD structure. The first plurality of interconnect layers and the second plurality of interconnect layers couple the first memory device and the second memory device to the control device.

The present disclosure, in some embodiments, relates to an integrated circuit. The integrated circuit includes a dielectric protection layer disposed over a dielectric structure that laterally surrounds one or more conductive interconnect layers. The dielectric protection layer has a protrusion extending outward from an upper surface of the dielectric protection layer. A bottom electrode is disposed over the dielectric protection layer and has sidewalls extending outward from a lower surface of the bottom electrode through the dielectric protection layer. The bottom electrode has a substantially planar upper surface over the protrusion. A data storage element is over the substantially planar upper surface of the bottom electrode, and a top electrode is over the data storage element.

The present disclosure relates to a resistive random access memory (RRAM) device. In some embodiments, the RRAM device has a bottom electrode disposed over a lower interconnect layer surrounded by an inter-level dielectric (ILD) layer. A dielectric data storage layer having a variable resistance is located above the bottom electrode, and a multi-layer top electrode is disposed over the dielectric data storage layer. The multi-layer top electrode has conductive top electrode layers separated by an oxygen barrier structure configured to mitigate movement of oxygen within the multi-layer top electrode. By including an oxygen barrier structure within the top electrode, the reliability of the RRAM device is improved since oxygen is kept close to the dielectric data storage layer.

A circuit includes a memory array having a plurality of memory cells; a control logic circuit, coupled to the memory array, and configured to use a first voltage signal to cause a first memory cell of the plurality of memory cells to transition from a first resistance state to a second resistance state, and a second voltage signal to cause the first memory cell to transition from the second resistance state to a third resistance state; and a counter circuit, coupled to the control logic circuit, and configured to increment a count by one in response to the first memory cell's transition from the first to the second resistance state, and again increment the count by one in response to the first memory cell's transition from the second to the third resistance state.

The present disclosure relates to a memory circuit having a shared control device for access to target and complementary memory devices for improved differential sensing. The memory circuit has a control device arranged within a substrate and having a first terminal coupled to a source-line, a second terminal coupled to a word-line, and a third terminal. A first memory device has a first lower electrode separated from a first upper electrode by a first data storage layer. The first upper electrode is coupled to the third terminal and the first lower electrode is coupled to a first bit-line. A second memory device has a second lower electrode separated from a second upper electrode by a second data storage layer. The second upper electrode is coupled to the second bit-line and the second lower electrode is coupled to the third terminal.

Semiconductor device including memory and logic circuit having FETs with ferroelectric layer and manufacturing methods thereof

The present disclosure relates to a method of manufacturing a memory device. The method is performed by forming an inter-layer dielectric (ILD) layer over a substrate, and forming an opening within a dielectric protection layer over the ILD layer. A bottom electrode layer is formed within the opening and over the dielectric protection layer. A chemical mechanical planarization (CMP) process is performed on the bottom electrode layer to form a bottom electrode structure having a planar upper surface and a projection that protrudes outward from a lower surface of the bottom electrode structure to within the opening. A memory element is formed over the bottom electrode structure, and a top electrode is formed over the memory element.

Memory device having a single bottom electrode layer

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Taipei, Taiwan

Tong-Chern Ong