International Business Machines Corporation

Barcelona Supercomputing Center-centro Nacional De Supercomputacion

Barcelona Supercomputing Center

Tong Chen

Tao Zhang

Zehra Noman Sura

Kathryn Mary O'Brien

John Kevin O'Brien

Mark Richard Nutter

Brian King Flachs

Brad William Michael

John K P O'Brien

Alper Buyuktosunoglu

Richard Harold Boivie

Marc Gonzalez Tallada

Alexandre E Eichenberger

John Kevin Patrick O'Brien

Gururaj Saileshwar

Yaoqing Gao

Daniel Arthur Prener

Haibo Lin

Arpith C Jacob

Byoungro So

Eduard Ayguade

Xavier Martorell

Li Feng Zhang

Bishwaranjan Bhattacharjee

Parijat Dube

Lixin Zhang

Benjamin P Segal

Hyojin Sung

Kevin K O'Brien

Tian Jin

A method, system and apparatus for protecting a program from making out of bounds memory references, including determining whether an instruction makes out of bound references where the instruction that loads data from or stores data to a buffer refers to addresses that are outside the bounds of the buffer, and responsive to the determining that the instruction refers to addresses that are partially out of bounds, changing an execution of the load or the store including modifying the starting address specified in the instruction, a length of data specified in the instruction, or a value for an out of bounds reference to load or store data that is within the bounds of the buffer.

Safe execution of programs that make out-of-bounds references

A method, system and apparatus for providing bound information accesses in buffer protection, including providing one-to-one mapping between a general-purpose register and bound information in a BI (bound information) register, saving loaded bound information in the BI register for future use, providing integrity of the bound information in the BI register that is maintained along program execution, and providing a pro-active load of the bound information with one-bit extra control on load instruction of the BI register.

Optimize bound information accesses in buffer protection

A method, system and apparatus for protecting against out-of-bounds references, including storing an address of a buffer in a general register and storing bounds information (BI) for the buffer in a bounds information register, and when a content of the general register is used as an address in a load or store operation, using a content of the bounds information register to determine if the load or store is out of bounds.

Dedicated bound information register file for protecting against out-of-bounds memory references

Techniques facilitating hardware-based memory-error mitigation for heap-objects. In one example, a system can comprise a process that executes computer executable components stored in a non-transitory computer readable medium. The computer executable components comprise: an entry component; and a re-purpose component. The entry component can allocate an entry in a table to store bounds-information when an object is allocated in memory. The re-purpose component can re-purpose unused bits of an object address to store an index to the table entry.

Protecting against invalid memory references

Methods and systems for optimizing an application for a computing system having multiple distinct memory locations that are interconnected by one or more communication channels include determining one or more data handling properties for a data region in an application. One or more data handling policies for the data region are determined based on the one or more data handling properties. Data setup costs are determined for a scope in the application that uses the data region in different memory locations based on the one or more data handling properties. The application is optimized in accordance with the one or more data handling policies and the data setup costs for the different memory locations.

Flexible optimized data handling in systems with multiple memories

In an approach to protecting against out-of-bounds buffer references, an apparatus comprises one or more processor cores and a bounds-checking functional unit in each processor core configured to manage bounds information for one or more memory buffers. When a buffer is allocated, an address range of the buffer is stored. When a pointer is assigned an address within the address range of the buffer, the address range of the buffer is associated with the pointer. When the pointer is used to compute an address for an operation, whether the address for the operation is within the address range associated with the pointer is determined. If the address is not within the address range associated with the pointer, signaling that an error has occurred.

Protecting against out-of-bounds buffer references

A method, system and apparatus for protecting from out of bounds memory references, including establishing a threshold number of active objects for examination for an out of bounds memory reference, determining whether a number of active objects for an application exceeds the threshold, and when the number of active objects exceeds the threshold, storing at least part of information about the active objects in an overflow table in a memory.

Hardware support for memory safety with an overflow table

Embodiments for implementing mixed precision learning for neural networks by a processor. A neural network may be replicated into a plurality of replicated instances and each of the plurality of replicated instances differ in precision used for representing and determining parameters of the neural network. Data instances may be routed to one or more of the plurality of replicated instances for processing according to a data pre-processing operation.

Data driven mixed precision learning for neural networks

Embodiments for program optimization are provided. A program is compiled with respect to a performance result utilizing a set of parameters. Information associated with the compiling of the program is collected. The collected information is external to the performance result. The set of parameters is changed based on the collected information.

Methods and systems for program optimization utilizing intelligent space exploration

Mechanisms are provided for arranging binary code to reduce instruction cache conflict misses. These mechanisms generate a call graph of a portion of code. Nodes and edges in the call graph are weighted to generate a weighted call graph. The weighted call graph is then partitioned according to the weights, affinities between nodes of the call graph, and the size of cache lines in an instruction cache of the data processing system, so that binary code associated with one or more subsets of nodes in the call graph are combined into individual cache lines based on the partitioning. The binary code corresponding to the partitioned call graph is then output for execution in a computing device.

Arranging binary code based on call graph partitioning

Software-managed resources are used to utilize effective-to-real memory address translation for synchronization among processes executing on processor cores in a multi-core computing system. A failure to find a pre-determined effective memory address translation in an effective-to-real memory address translation table on a first processor core triggers an address translation exception in a second processor core and causes an exception handler on the second processor core to start a new process, thereby acting as a means to achieve synchronization among processes on the first processor core and the second processor core. The specific functionality is implemented in the exception handler, which is tailored to respond to the exception based on the address that generated it.

Method to efficiently implement synchronization using software managed address translation

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Yorktown Heights, NY, United States of America

Tong Chen