Beijing University of Technology

Tong An

Fei Qin

Wei Wu

Rui Zhou

Pei Chen

Shuai Zhao

Guofeng Xia

Chengyan Liu

Wenhui Zhu

Yanwei Dai

Lixiang Zhang

Xueheng Zheng

Yakun Zhang

Disclosed are a device and a method for measuring a fretting displacement in a power cycling of a press-pack insulated gate bipolar transistor (IGBT). The IGBT includes: a bracket; slide bars slidably mounted on the bracket and are arranged at least four along a circumferential direction of the bracket; sensors respectively slidably installed on the bracket and the slide bars; and a power cycling experiment device arranged inside the bracket.

Device and method for measuring fretting displacement in power cycle of press-pack IGBT

Disclosed is a pressure balancing clamp for a press-pack insulated gate bipolar transistor (IGBT) module. The pressure balancing clamp for a press-pack IGBT module includes a bracket, where the bracket is provided with two longitudinally arranged pressure equalizing plates in a sliding way; the pressure equalizing plates are connected through pressure sensors; the upper and lower ends inside the bracket are respectively connected with the pressure equalizing plates through hydraulic devices and a displacement compensation device; opposite surfaces of the two pressure equalizing plates are respectively provided with heat dissipation and confluence devices. The pressure sensors are in one-to-one correspondence with the hydraulic devices and are electrically connected. The hydraulic devices adjust the pressure according to the readings of the pressure sensors in corresponding directions, so that the pressure of the press-pack IGBT module is balanced.

Pressure balancing clamp for press-pack insulated gate bipolar transistor module

A method and apparatus for on-line measurement of the wafer thinning and grinding force, related to the field of ultra-precision machining of semiconductor wafer materials. The grinding force measuring apparatus comprises a semiconductor wafer, a worktable, a bearing table, a thin film pressure sensor, and a data processing and wireless transmission module. The grinding force measuring method includes sensor calibration based on the testing device and on-line measurement of grinding force. Using the grinding force measuring device and method provided by the invention, the grinding force in the semiconductor wafer grinding process can be monitored in real time, which is of great significance for semiconductor processing and reducing grinding damage. The invention also has the following characteristics: the sensor adopts a film pressure sensor, the response time is short, and the test precision is high; the data transmission adopts a wireless transmission design, thus the grinding force can be monitored in real time during the wafer and spindle rotation process and the risk of winding during wafer rotation can be avoided. The sensor adopts a distributed design, which can monitor the distribution of the grinding force along the wafer radial direction or crystal orientation.

Device and method for on-line measurement of wafer grinding force

The invention discloses a packaging structure and manufacturing method of a SiC MOSFET module, which is composed of SiC MOSFET chips, upper DBC substrate, lower DBC substrate, ceramic interposer, silicon oxide dielectric layer, nano silver pastes, redistribution layer, through-ceramic-hole conductive metals and power terminals. The SiC MOSFET chips are connected to the lower DBC substrate using nano silver pastes in the invention. Besides, some rectangular frames are made on the ceramic interposer, and the SiC MOSFET chips are embedded in the ceramic interposer by filling dielectric materials. The upper surfaces of the chips and the ceramic interposer are covered with a conductive metal redistribution layer, and the upper and lower surfaces of the ceramic interposer are interconnected with the upper and lower DBC substrates, respectively. The power terminals are led out from the conductive copper layers of the upper and lower DBC substrates. This invention can realize the high-temperature packaging of SiC MOSFET modules. By introducing double-sided heat dissipation, the thermal performance can be improved effectively. The parasitic inductance of the module can be also reduced by using planar interconnection instead of wire bonding.

Packaging structure of a SiC MOSFET power module and manufacturing method thereof

A manufacturing method for Package in Package (PiP) electronic device based on multi-row Quad Flat No-lead (QFN) package is provided wherein the lower surface of plate metallic base material are half-etched to form grooves. Insulation filling material is filled in the half-etched grooves. The upper surface of plate metallic base material is half-etched to form chip pad and multi-row of leads. Encapsulating IC chip for wire bonding, adhesive material, metal wire, chip pad and a plurality of leads to form a multi-row QFN package as an inner package. Flip-chip bonding IC chip with solder bumps on the first metal material layer of leads. Encapsulating IC chip with solder bumps, the multi-row QFN package, adhesive material, and leads to form an array of PiP electronic devices. Sawing and separating the PiP electronic device array, forming PiP electronic device unit.

Package in package (PiP) electronic device and manufacturing method thereof

A manufacturing method for Flip Chip on Chip (FCoC) package based on multi-row Quad Flat No-lead (QFN) package is provided wherein the lower surface of plate metallic base material are half-etched to form grooves. Insulation filling material is filled in the half-etched grooves. The upper surface of plate metallic base material is half-etched to form chip pad and multi-row of leads. Encapsulating first IC chip, second IC chip, solder bumps, underfill material, and metal wire to form an array of FCoC package based on the type of multi-row QFN package. Sawing and separating the FCoC package array, and forming FCoC package unit.

Growing community of inventors

Beijing, China

Tong An