Nec Corporation

Renesas Electronics Corporation

Nec Electronics Corporation

Tomoyuki Yamase

Tadashi Maeda

Shinichi Hori

Hidemi Noguchi

Masaaki Tanio

Noriaki Matsuno

Tomonobu Kurihara

Yuu Yamaguchi

Orie Tsuzuki

Yoshinori Horiguchi

Isao Sakakida

Junichi Abe

Hitoshi Yano

Keiichi Numata

Yasushi Amamiya

This transmitter is provided with: a digital delay circuit which delays a 1-bit digital RF signal on the basis of another 1-bit digital RF signal; an amplifier which amplifies a signal output by the digital delay circuit; and a band-pass filter which allows signals in a prescribed frequency band, from among signals output by the amplifier, to pass. A signal output by the band-pass filter is input into a corresponding one antenna element from among a plurality of antenna elements, and controls the directionality of a beam formed by the plurality of antenna elements.

Transmitter and method of controlling transmitter

The purpose of the present invention is to provide an amplifier having high signal-to-noise ratio of a transmitted signal and high electrical efficiency. Another purpose is to suppress complexity of amplifier's wiring connecting a signal generator that generates a binary digital signal and an amplification unit that amplifies the same. This amplifier generates a binary digital signal. The amplifier further generates a K-value digital signal (K is an integer greater than or equal to 3) from the binary digital signal and generating a plurality of binary digital signals from the K-value digital signal. The amplifier amplifies each of the plurality of binary digital signals, and combines the plurality of amplified binary digital signals and generating a combined signal having a substantially proportional relationship with the K-value digital signal.

Amplifier and transmitter, and transmission method

This &#x394;&#x3a3; modulator is a &#x394;&#x3a3; modulator using multiple integrators. The integrator: includes a plurality of stages of adder sequences, each of the adder sequences including a plurality of adders connected in series; performs feedback of a result of a second adder sequence as an input to a first adder sequence, the first adder sequence being a first stage of the plurality of stages, and the second adder sequence being a last stage of the plurality of stages; and processes inputs supplied to the plurality of adders of the first adder sequence and supplies it to the second adder sequence.

Delta-sigma modulator, transmitter, and integrator

In a digital transmitter, a digital RF signal generation unit executes digital modulation on I and Q signals to convert the I and Q signal into first and second digital RF signals, respectively, with a bit rate which is twice a carrier frequency. A retiming unit delays the first digital RF signal according to a clock signal with a frequency which is 4n times (n is an integer) the carrier frequency to output the delayed first digital RF signal and delays the phase of the second digital RF signal by 90 degrees with respect to an output of the first digital RF signal to output the delayed second digital RF signal. First and second amplifiers amplify the first and second digital RF signals output by the retiming unit, respectively. A combiner combines the amplified first and second digital RF signals to generate one signal sequence.

Digital transmitter

Provided are a wireless access system provided with a remote unit capable of handling a high-frequency region without being made complicated, and a control method for the same. A wireless access system according to the present invention is provided with: a center unit (); and a remote unit () that converts a baseband signal generated by the center unit () into a high-frequency signal and emits the high-frequency signal from an antenna (). The center unit () includes a 1-bit modulator () that converts the baseband signal into a 1-bit signal on the basis of a generated clock signal and outputs the 1-bit signal. The remote unit () includes: a local generation unit () that extracts the clock signal from the 1-bit signal output from the center unit (), and generates a local signal using the extracted clock signal as a reference signal; a filter () that extracts a desired band component from the 1-bit signal; and an up-converter () that converts, using the local signal, an output signal of the filter into a high-frequency signal.

Wireless access system and control method for same

To adequately perform sampling, a receiving device that solves problems that involve an increase in circuit area and an increase in cost, is provided. A/D convertersamples a coherent signal that is an analog signal in synchronization with a sampling clock signal so as to convert the analog signal into a digital signal. DSPdemodulates the digital signal converted by A/D converterand computes a phase of the sampling clock signal in which an error rate of the digital signal is the minimum based on the demodulated digital signal. Sampling clock extraction circuitextracts a clock signal having a symbol rate of the coherent signal therefrom. Phase adjustment circuitadjusts the phase of the clock signal extracted by sampling clock extraction circuitto the phase computed by DSPand generates a clock signal having the adjusted phase as the sampling clock signal.

Receiving device and demodulation device

An A/D conversion unit performs an A/D conversion operation twice during a hold period of an analog value. In a first conversion operation, the A/D conversion unit compares the analog value with a first reference voltage and outputs a comparison result as first converted data. In a second conversion operation, the A/D conversion unit compares the analog value with a second reference voltage and outputs a comparison result as second converted data. The second reference voltage is a voltage obtained by adding or subtracting a minimum resolution voltage to or from the first reference voltage. A digital processing unit averages errors of the first and second converted data by digital processing to detect an A/D conversion error, and feeds back a detection result to the A/D conversion unit as a control value to perform voltage control.

A/D conversion device and A/D conversion correcting method

An analog-to-digital conversion device which converts an analog input signal into a digital signal and output it includes a signal characteristic detection unit for detecting a predetermined characteristic of the input signal; a control signal generation unit for setting a resolution based on the signal characteristic detected by the signal characteristic detection unit, generating a control signal that indicates only an operation required for performing the analog-to-digital conversion at the resolution, and outputting it; and an analog-to-digital conversion unit for restricting the operation based on the control signal and converting the input signal into the digital signal at the set resolution.

Analog-to-digital conversion device and analog-to-digital conversion method

A non-linear effect of a rectifier element is enhanced, an input amplitude is increased by further taking advantage of a resonance circuit, and a rectification efficiency of a rectifier circuit for detection is improved, so that the gain of an amplifier circuit at a latter stage can be set low. RF input terminalsare applied with signals at phases opposite to each other. A signal at terminalis applied to a gate of transistor Mthrough capacitor C, and a signal at terminalis applied to node Nconnected with a source of transistor Mand a gate and a drain of transistor Mthrough capacitor Cdesignate terminals applied with DC biases, and L, Cand L, Care series resonance circuits. Half-wave double voltage rectifier circuits comprised of M, M, C-C, Rare connected in cascade at a plurality of stages.

Start signal detector circuit

Provided is an electronic circuit system which facilitates skew timing adjustment while preventing increase of power consumption. An electronic circuit system includes: a track hold circuit module formed by a hierarchical tree structure of track hold circuits which can track-hold an analog value of an analog signal; and a control signal generation module which supplies an operation control signal to each of the track hold circuits in the hierarchical tree structure. In the hierarchical tree structure, the number of track hold circuits of each of the hierarchies is stepwise changed from the first hierarchy of the input side to which an analog signal is inputted, toward the final hierarchy of the final output side as the number of hierarchies is increased.

Electronic circuit system, track hold circuit module, electronic circuit operation control method, and program thereof

An information storage device includes a storage that stores transfer data from an information processing device, the information storage device being removably connected to the information processing device, a switch unit that switches a data transfer mode of the information processing device in accordance with manipulation by a user, and a controller that controls the information processing device to transfer data in a mode in which data temporarily stored in a data storing area is transferred to the storage or in a mode in which data is transferred to the storage without being temporarily stored in the data storing area in accordance with the selection of the data transfer mode by the switch unit.

Information storage device, information processing system, and setting method of data transfer mode of information processing device

A signal processing device includes a detecting part that detects intensity of an input signal, a timer part that includes a time constant circuit and measures time based on a time constant of the time constant circuit, and a determination circuit that counts the number of times of switching of the input signal detected by the detecting part within the time measured by the time constant circuit.

Signal processing device

The present invention is aimed at realizing an amplifying circuit whose chip size is prevented from being significantly increased even if the number of compatible frequencies increases, and which has a wide dynamic range when it operates under a low voltage. The amplifying circuit includes a plurality of impedance converting circuits connected to each other by a switching circuit of a first type having a signal cutting-off function, a switching circuit of a second type connected to a path branched from an input side of the switching circuit of the first type, the switching circuit of the second type having a signal cutting-off function, amplifiers connected respectively to an output side of one of the impedance converting circuits in a final stage and to an output side of the switching circuit of the second type, and a control signal generating circuit for controlling connection/disconnection between said switching circuit of the first type and said switching circuit of the second type; wherein either one of the paths is selected to input a signal to one of the amplifiers.

Amplification circuit

A variation of a threshold of diode-connected transistors is compensated for to maintain a constant rectification efficiency of a rectifier circuit, thereby enabling stable detection of a start signal. A constant voltage is applied to DC bias terminalof cascaded half-wave voltage doubler rectifier circuits (including MOS transistors Mto Mand capacitors Cto C) forming a rectifier circuit, and a voltage equal to the sum of the constant voltage applied to DC bias terminaland a variation &#x394;Vt of a threshold voltage of the MOS transistors is applied to DC bias terminalof cascaded half-wave voltage doubler rectifier circuits (including MOS transistors Mto Mand capacitors Cto C) forming a bias circuit.

The present invention provides an amplifying circuit capable of accomplishing high-impedance input/output, and providing a high gain and low power consumption. The amplifier amplifies a signal received through an input terminal, and outputs the signal through an output terminal. A control circuit comprised of the inductors, and the switches turns input/output impedances of the amplifier into a high impedance.

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Tokyo, Japan

Tomoyuki Yamase