Socionext Inc.

Fujitsu Semiconductor Limited

Fujitsu Corporation

Tomoyuki Yamada

Tomoharu Awaya

Takayoshi Minami

Shigetoshi Takeda

Koji Banno

Fumio Ushida

Tsuyoshi Sakata

Toshio Hino

Toyoji Sawada

Masayuki Nakada

Kazuo Sukegawa

Yoshikazu Arisaka

Yusuke Tanefusa

Tomoya Tsuruta

Tsutomu Tatematsu

Morimi Arita

Kengi Togashi

Norihiro Harada

A semiconductor storage device includes first and second memory cells adjacent to each other in the X direction, each of the memory cells having a program transistor and a switch transistor. First and second nanosheets, which are to be channel regions of the program transistors, are exposed from first and second gate interconnects, respectively, at faces on the sides opposed to each other in the X direction. Third and fourth nanosheets, which are to be channel regions of the switch transistors, are exposed from third and fourth gate interconnects, respectively, at faces on the sides opposed to each other in the X direction.

Semiconductor storage device

A layout structure of a small-area one time programmable (OTP) memory using a complementary FET (CFET) is provided. The OTP memory has transistors TP as a program element and transistors TS as a switch element. The transistors TP are three-dimensional transistors of which channel portions overlap each other as viewed in plan. The transistors TS are three-dimensional transistors of which channel portions overlap each other as viewed in plan. The OTP memory of two bits is implemented in a small area.

A nonvolatile memory cell using vertical nanowire (VNW) FETs includes a program element of which a gate is connected to a word line, and a switch element that is provided between the program element and a bit line and of which a gate is connected to the word line. The program element and the switch element are each constituted by one or a plurality of VNW FETs, and these VNW FETs are arranged in a line in a first direction.

A semiconductor device provided on a semiconductor substrate includes an element region including an element, a moisture-resistant frame surrounding the element region, an insulating layer provided between the moisture-resistant frame and an outer peripheral edge of the semiconductor device and on the semiconductor substrate, a first metal line extending along the outer peripheral edge and provided in the insulating layer, and a groove provided in the insulating layer.

Semiconductor device and method of producing semiconductor device

Characteristics of each transistor in a semiconductor device including a transistor of a memory cell are measured by an ASV monitoring circuit, a power supply voltage supplied to the semiconductor device is determined based on the measured characteristics of the transistor, a data read-out speed of the memory cell under the determined power supply voltage supplied is measured while changing a signal level of a word line by an SRAM word line monitoring circuit, the signal level of the word line is determined by comparing the measured data read-out speed of the memory cell and a specification range of the memory cell, and the signal level of the word line is appropriately set at the power supply voltage applied by the ASV.

Adjustment method of signal level in semiconductor device and semiconductor device

In an OTP memory storing a one-bit of the data by two gate insulating film destruction type nonvolatile memory cells where a same bit line is connected and different word lines are connected, writings and readings of the data for selected two nonvolatile memory cells constituting one-bit are performed by simultaneously selecting the selected two nonvolatile memory cells, and verifications for the selected two nonvolatile memory cells are performed by individually selecting one and the other of the selected two nonvolatile memory cells one by one.

Semiconductor device and control method thereof

A design support program stored in a recording medium readable by a computer includes acquiring a first analysis result including information about an area included in circuit information of a design target circuit and a second analysis result relating to a path of the circuit information, the temperature of the area being equal to or higher than a certain temperature; determining an arbitrary cell on a non-critical path from among cells arranged in the area as a target cell for decreasing the area temperature; and outputting a result of the determination.

Support program, design support device, and design support method

Semiconductor device, moisture-resistant frame, groove and method of producing semiconductor device

A simulation method to be implemented in a computer causes the computer to execute a procedure carrying out a weighting with respect to layout parameters of a circuit, which is an analyzing target, based on priority information of cells forming the circuit, and converting the weighted layout parameters into physical characteristics and storing the physical characteristics in a memory part, a procedure converting the physical characteristic read from the memory part into circuit parameters and storing the circuit parameters into the memory part, and analyzing the circuit based on a net list including the circuit parameters read from the memory part.

Simulation method and computer-readable storage medium

There is provided a layout verification method including a space acquisition step of, with a wiring connected to a gate through a via as a target wiring, acquiring a space between the target wiring and a wiring adjacent thereto, a calculation step of calculating an antenna ratio according to the space between the target wiring and the adjacent wiring, the area of the gate, and the area of the target wiring, and an output step of outputting an antenna damage error when the antenna ratio exceeds a predetermined value.

Layout verification method and device

A high-strength protective member made of tungsten is disposed under a disconnecting point of a fuse. This protective member is formed simultaneously with formation of a via contact portion which connects the fuse with wiring, for example.

Growing community of inventors

Kawasaki, Japan

Tomoyuki Yamada