Sumitomo Chemical Company, Limited

National Institute of Advanced Industrial Science and Technology

The University of Tokyo

Tomoyuki Takada

Masahiko Hata

Yasushi Iyechika

Yoshinobu Ono

Sadanori Yamanaka

Katsumi Inui

Noboru Fukuhara

Taro Itatani

Kenji Kohiro

Masaya Shimizu

Toshihisa Katamime

Shinichi Takagi

Hisashi Yamada

Taketsugu Yamamoto

Mitsuru Takenaka

Kazumasa Ueda

Yoshihiko Tsuchida

Takenori Osada

Osamu Ichikawa

Yuichi Hiroyama

Kazumi Wada

Hiroyuki Ishii

Eiji Kume

Kazuhiko Honjo

Jaehoon Han

Toshihisa Katamine

Masao Shimada

There is provided a fabrication technique of a MOS structure that has a small EOT without increasing the interface trap density. More specifically, provided is a method of producing a semiconductor wafer that includes a semiconductor crystal layer, an interlayer made of an oxide, nitride, or oxynitride of a semiconductor crystal constituting the semiconductor crystal layer, and a first insulating layer made of an oxide and in which the semiconductor crystal layer, the interlayer, and the first insulating layer are arranged in the stated order. The method includes (a) forming the first insulating layer on an original semiconductor crystal layer, and (b) exposing a surface of the first insulating layer with a nitrogen plasma to nitride, oxidize, or oxynitride a part of the original semiconductor crystal layer, thereby forming the interlayer, together with the semiconductor crystal layer that is the rest of the original semiconductor crystal layer.

Method of producing semiconductor wafer, semiconductor wafer, method of producing semiconductor device and semiconductor device

There is provided a semiconductor wafer including a base wafer whose surface is entirely or partially a silicon crystal plane, an inhibitor positioned on the base wafer to inhibit crystal growth and having an opening that reaches the silicon crystal plane, a first crystal layer made of SiGe(0&#x2266;x&#x3c;1) and positioned on the silicon crystal plane that is exposed in the opening, a second crystal layer positioned on the first crystal layer and made of a III-V Group compound semiconductor that has a band gap width larger than a band gap width of the first crystal layer, and a pair of metal layers positioned on the inhibitor and the second crystal layer. The pair of the metal layers are each in contact with the first crystal layer and the second crystal layer.

Semiconductor wafer, semiconductor device, and method of producing semiconductor wafer

Electronic device is provided, including: a base wafer whose surface is made of silicon crystal; a Group 3-5 compound semiconductor crystal formed directly or indirectly on partial region of the silicon crystal; an electronic element including a portion of the Group 3-5 compound semiconductor crystal as active layer; an insulating film formed directly or indirectly on the base wafer and covering the electronic element; an electrode formed directly or indirectly on the insulating film; a first coupling wiring extending through the insulating film, having at least a portion thereof formed directly or indirectly on the insulating film, and electrically coupling the electronic element with the electrode; a passive element formed directly or indirectly on the insulating film; a second coupling wiring extending through the insulating film, having at least a portion thereof formed directly or indirectly on the insulating film, and electrically coupling the electronic element with the passive element.

Electronic device and method for producing electronic device

A sensor includes: a base wafer containing silicon; a seed member provided directly or indirectly on the base wafer; and a photothermal absorber that is made of a Group 3-5 compound semiconductor lattice-matching or pseudo lattice-matching the seed member and being capable of generating a carrier upon absorbing light or heat, where the photothermal absorber outputs an electric signal in response to incident light to be introduced into the photothermal absorber or heat to be applied to the photothermal absorber. A semiconductor wafer includes: a base wafer containing silicon; a seed member provided directly or indirectly on the base wafer; and a photothermal absorber that is made of a Group 3-5 compound semiconductor lattice-matching or pseudo lattice-matching the seed member and being capable of generating a carrier upon absorbing light or heat.

Sensor, semiconductor wafer, and method of producing semiconductor wafer

The semiconductor wafer includes: a base wafer; and an inhibition layer that is disposed on the base wafer as one piece or to be separate portions from each other, and inhibits growth of a crystal of a compound semiconductor, where the inhibition layer has a plurality of first opening regions that have a plurality of openings penetrating the inhibition layer and leading to the base wafer, each of the plurality of first opening regions includes therein a plurality of first openings disposed in the same arrangement, some of the plurality of first openings are first element forming openings each provided with a first compound semiconductor on which an electronic element is to be formed, and the other of the plurality of first openings are first dummy openings in which no electronic element is to be formed.

Semiconductor wafer, method of producing semiconductor wafer, electronic device, and method of producing electronic device

A high-quality GaAs-type crystal thin film using an inexpensive Si wafer with good thermal release characteristics is achieved. Provided is a semiconductor wafer comprising an Si wafer; a Ge layer that is crystal-grown on the wafer and shaped as an isolated island; a buffer layer that is crystal-grown on the Ge layer and is a group 3-5 compound semiconductor layer containing P; and a functional layer that is crystal-grown on the buffer layer. The Ge layer may be shaped as an island having a size that does not exceed double a distance moved by crystal defects as a result of annealing the Ge layer at a certain temperature for a certain time. The Ge layer may be shaped as an island having a size for which stress due to a difference relative to a thermal expansion coefficient of Si, which is material of the wafer, does not cause crystal defects when the Ge layer is annealed at a certain temperature.

Semiconductor wafer, semiconductor wafer manufacturing method, and electronic device

A high-quality GaAs-type crystal thin film using an inexpensive Si wafer with good thermal release characteristics is achieved. Provided is a semiconductor wafer comprising an Si wafer; an inhibiting layer that is formed on the wafer and that inhibits crystal growth, the inhibiting layer including a covering region that covers a portion of the wafer and an open region that does not cover a portion of the wafer within the covering region; a Ge layer that is crystal-grown in the open region; a buffer layer that is crystal-grown on the Ge layer and is a group 3-5 compound semiconductor layer containing P; and a functional layer that is crystal-grown on the buffer layer. The Ge layer may be formed then annealing with a temperature and duration that enables movement of crystal defects.

Semiconductor wafer including lattice matched or pseudo-lattice matched buffer and GE layers, and electronic device

The objective is to improve capabilities such as high-speed switching of a compound semiconductor device. Provided is a semiconductor wafer comprising a silicon wafer; an insulating film that is formed on the silicon wafer and that has an open portion reaching the silicon wafer; a Ge crystal formed in the open portion; a seed compound semiconductor crystal that is grown with the Ge crystal as a nucleus and that protrudes beyond a surface of the insulating film; and a laterally grown compound semiconductor layer that is laterally grown on the insulating film with a specified surface of the seed compound semiconductor crystal as a seed surface.

Semiconductor wafer, method of manufacturing a semiconductor wafer, and electronic device

A semiconductor wafer including: a base wafer; a seed crystal disposed on the base wafer; a compound semiconductor disposed above the seed crystal; and a high resistance layer disposed between the seed crystal and the compound semiconductor, the high resistance layer having a larger resistivity than the seed crystal, and the seed crystal lattice matching or pseudo lattice matching the compound semiconductor is provided.

Semiconductor substrate, electronic device and method for manufacturing semiconductor substrate

A high-quality GaAs-type crystal thin film using an inexpensive Si wafer with good thermal release characteristics is achieved. Provided is a semiconductor wafer comprising an Si wafer; an inhibiting layer that is formed on the wafer and that inhibits crystal growth, the inhibiting layer including a covering region that covers a portion of the wafer and an open region that does not cover a portion of the wafer within the covering region; a Ge layer that is crystal-grown in the open region; and a functional layer that is crystal-grown on the Ge layer. The Ge layer may be formed by annealing with a temperature and duration that enables movement of crystal defects, and the annealing is repeated a plurality of times.

There is provided a method of producing a semiconductor wafer by thermally processing a base wafer having a portion to be thermally processed that is to be thermally processed. The method comprises a step of providing, on the base wafer, a portion to be heated that generates heat through absorption of an electromagnetic wave and selectively heats the portion to be thermally processed, a step of applying an electromagnetic wave to the base wafer, and a step of lowering the lattice defect density of the portion to be thermally processed, by means of the heat generated by the portion to be heated through the absorption of the electromagnetic wave.

Method for producing semiconductor substrate, semiconductor substrate, method for manufacturing electronic device, and reaction apparatus

Provided is an optical device including a base wafer containing silicon, a plurality of seed crystals disposed on the base wafer, and a plurality of Group 3-5 compound semiconductors lattice-matching or pseudo lattice-matching the plurality of seed crystals. At least one of the Group 3-5 compound semiconductors has a photoelectric semiconductor formed therein, the photoelectric semiconductor including a light emitting semiconductor that emits light in response to a driving current supplied thereto or a light receiving semiconductor that generates a photocurrent in response to light applied thereto, and at least one of the plurality of Group 3-5 compound semiconductors other than the Group 3-5 compound semiconductor having the photoelectric semiconductor has a heterojunction transistor formed therein.

Optical device and semiconductor wafer

To improve the flatness of the surface and improve the reliability of a semiconductor device when expitaxially growing semiconductor crystal layers of different types on a single silicon wafer, provided is a semiconductor wafer which includes: a base wafer having a silicon crystal in the surface thereof, the silicon crystal having a first dent and a second dent; a first Group IVB semiconductor crystal located in the first dent and exposed; a second Group IVB semiconductor crystal located in the second dent; and a Group III-V compound semiconductor crystal located above the second Group IVB semiconductor crystal in the second dent and exposed.

Semiconductor wafer, semiconductor device, and method for producing semiconductor wafer

A compound semiconductor epitaxial substrate and a process for producing the same are provided. The compound semiconductor epitaxial substrate comprises a single crystal substrate, a lattice mismatch compound semiconductor layer and a stress compensation layer, wherein the lattice mismatch compound semiconductor layer and the stress compensation layer are disposed on the identical surface side of the single crystal substrate, there is no occurrence of lattice relaxation in the lattice mismatch compound semiconductor layer, as well as the stress compensation layer, and Ls representing the lattice constant of the single crystal substrate, Lm representing the lattice constant of the lattice mismatch compound semiconductor layer, and Lc representing the lattice constant of the stress compensation layer satisfy the formula (1a) or (1b).Lm Lm&#x3e;Ls&#x3e;Lc&#x2003;&#x2003;(2a)

Compound semiconductor epitaxial substrate and process for producing the same

A method for manufacturing a compound semiconductor epitaxial substrate with few concave defects is provided. The method for manufacturing a compound semiconductor epitaxial substrate comprises a step of epitaxially growing an InGaAs layer on an InP single crystal substrate or on an epitaxial layer lattice-matched to the InP single crystal substrate under conditions of ratio of V/: 10-100, growth temperature: 630&#xb0; C.-700&#xb0; C., and growth rate: 0.6 &#x3bc;m/h-2 &#x3bc;m/h.

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Tsukuba, Japan

Tomoyuki Takada