Fujitsu Corporation

Tomoyuki Okawa

Masaki Ukai

Hiroyuki Kojima

Mie Tonosaki

Kuniki Morita

Hideki Sakata

Souta Kusachi

Kumiko Endo

To reduce the number of bits required for LRU control when the number of target entries is large, and achieve complete LRU control. Each time an entry is used, an ID of the used entry is stored to configure LRU information so that storage datastored in the leftmost position indicates an ID of an entry with the oldest last use time (that is, LRU entry), for example as shown in FIG.(). An LRU control apparatus according to a first embodiment of the present invention refers to the LRU information, and selects an entry corresponding to the storage data(for example, entry) from the LRU information as a candidate for the LRU control, based on the storage dataas the ID of the entry with the oldest last use time.

Method for updating information used for selecting candidate in LRU control

A cache controller controls at least one cache. The cache includes ways including a plurality of blocks that stores therein entry data. A writing unit writes degradation data to a failed block. The degradation data indicates that the failed block is in a degradation state. A reading unit reads entry data from a block. A determining unit determines, if the entry data obtained by the reading unit includes the degradation data, that the block is in the degradation state.

Method and apparatus for controlling degradation data in cache

A degeneration control device that controls degeneration of a cache having a plurality of ways based on an error that occurs in response to an access request, includes a cache line degeneration information memory unit, which stores cache line degeneration information that indicates whether a cache line constituting each of the plurality of ways is degenerated, and a degeneration control unit, which writes, when an error that occurs in response to the access request causes a predetermined condition to be met, cache line degeneration information that indicates a predetermined cache line where the error occurs is degenerated in the cache line degeneration information memory unit.

Degeneration control device and degeneration control program

A cache-memory control apparatus controls a level-1 (L1) cache and a level-2 (L2) cache having a cache line divided into a plurality of sub-lines for storing data from the L1 cache. The cache-memory control apparatus includes a control-flag adding unit, an L1 cache control unit, and an L2 cache control unit. The control-flag adding unit provides an SP flag to each of the sub-lines. The L1-cache control unit acquires an access virtual address, and, when there is no data at the access virtual address, outputs an L2 cache-access address to the L2-cache control unit. The L2-cache control unit switches the SP flag based on a virtual page number in an L1 index and a physical page number in an L2 index. Based on the SP flag, corresponding one of the sub-lines is written back to the L1 cache.

Cache-memory control apparatus, cache-memory control method and computer product

A cacheable memory access space receives memory access addresses having different data structures according to a status of a cache capacity from a processor. A cache hit detector determines whether data has been hit based on a mode signal, an enbblk [n] signal, and a signal indicating whether the way is valid or invalid, which are preset in the cache hit detector, a tag comparison address received from the cacheable memory access space, and a tag received from the storage unit.

Cache memory and method of controlling memory

A cache memory includes a first-level cache-memory unit that stores data; a second-level cache-memory unit that stores data that is same as the data stored in the first-level cache-memory unit; a storage unit that stores a part of information relating to the first-level cache-memory unit; and a coherence maintaining unit that maintains cache-coherence between the first-level cache-memory unit and the second-level cache-memory unit based on information stored in the storage unit.

Cache memory and method to maintain cache-coherence between cache memory units

A circuit for driving and controlling a second cache that is incorporated in a processor and comprises a plurality of RAM. The circuit comprises a second-cache control unitA and a chip-enable control unit. The second-cache control unitA receives an access request for an access to the second cache and designates some of the RAMs, which need not operate, in accordance with the type or address of the access request, or both. The chip-enable control unitoutputs an intra-macro stop-instructing signal to the RAMs that have been designated by the second-cache control unitA.

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Kawasaki, Japan

Tomoyuki Okawa