Panasonic Corporation

Matsushita Electric Industrial Co., Ltd.

Tomoyuki Nakayama

Koji Takemura

Noriyuki Nagai

Atsushi Doi

Hoyeun Huh

Manabu Ohnishi

Shoichi Tanaka

Kenji Furumoto

Tugio Murayama

Mikiya Mai

Kenro Jitsumori

Input/output cells are formed so as to be peripherally arranged adjacent to a corner cell on a surface of a semiconductor chip, and electrode pads are formed on the respective input/output cells. The electrode pads are configured in a zigzag pad arrangement so as to form inner and outer pad arrays. However, of the electrode pads forming the inner pad array, those electrode pads in predetermined areas adjacent to the two sides of the corner cell are not disposed, such that an interconnect pattern of a carrier which is bump-bonded to the semiconductor chip and vias are prevented from becoming complex.

Semiconductor device having a pad-disposition restriction area

Semiconductor device

A testing board for testing the electric characteristics of semiconductor integrated circuit elements by applying a voltage to each of the testing electrodes of the semiconductor integrated circuit elements comprises a wiring board having a wiring layer at the surface thereof opposing the semiconductor integrated circuit elements. An elastic sheet is disposed in spaced relation to the opposing surface of the wiring board. Probe terminals are disposed on the surface of the elastic sheet opposing the semiconductor integrated circuit elements to correspond to the testing electrodes. A conductive wire has both end portions joined to the wiring layer of the wiring board and a middle portion spaced from the opposing surface of the wiring board. An elastic member for biasing the conductive wire such that the middle portion of the conductive wire is brought into contact with the probe terminal is disposed between the wiring board and the conductive wire.

Testing Board

Growing community of inventors

Osaka, Japan

Tomoyuki Nakayama