Hitachi, Ltd.

Hitachi Power Semiconductor Device, Ltd.

Tomoyuki Miyoshi

Yohei Yanagida

Mutsuhiro Mori

Masaki Shiraishi

Shinichiro Wada

Tomoyasu Furukawa

Yujiro Takeuchi

Takayuki Oshima

Hiroki Kimura

So Watanabe

Kenji Miyakoshi

Yusuke Hotta

A semiconductor device having a high cutoff resistance capable of suppressing local current/electric field concentration and current concentration at a chip termination portion due to an electric field variation between IGBT cells due to a shape variation and impurity variation during manufacturing. The semiconductor device is characterized by including an emitter electrode formed on a front surface of a semiconductor substrate via an interlayer insulating film, a collector electrode formed on a back surface of the semiconductor substrate, a first semiconductor layer of a first conductivity type in contact with the collector electrode, a second semiconductor layer of a second conductivity type, a central area cell, and an outer peripheral area cell located outside the central area cell.

Semiconductor device and power conversion device

A current switching semiconductor device to be used in a power conversion device achieves both a low conduction loss and a low switching loss. The semiconductor device includes the IGBT in which only Gc gates are provided and an impurity concentration of the p type collector layer is high, and the IGBT in which the Gs gates and the Gc gates are provided and an impurity concentration of the p type collector layer is low. When the semiconductor device is turned off, the semiconductor device transitions from a state in which a voltage lower than a threshold voltage is applied to both the Gs gates and the Gc gates to a state in which a voltage equal to or higher than the threshold voltage is applied to the Gc gates prior to the Gs gates.

The invention provides an inexpensive flywheel diode having a low power loss. A semiconductor substrate side of a gate electrode provided on a surface of an anode electrode side of a semiconductor substrate including silicon is surrounded by a p layer, an n layer, and a p layer via a gate insulating film. The anode electrode is in contact with the p layer with a low resistance, and is also in contact with the n layer or the p layer, and a Schottky diode is formed between the anode electrode and the n layer or the p layer.

To provide a semiconductor device in which an IGBT having two gate terminals is driven by one control signal, and a continuous ON state and an ON state twice for one on-pulse signal are avoided. A semiconductor device includes: a control signal input terminal; an IGBT having a first gate terminal and a second gate terminal; a delay unit configured to delay an input signal for a delay time; and a logical product unit configured to calculate a logical product of a first input terminal and a second input terminal. The control signal input terminal is connected to an input terminal of the delay unit and a second input terminal of the logical product unit. An output terminal of the delay unit is connected to the first gate terminal of the IGBT and a first input terminal of the logical product unit. An output terminal of the logical product unit is connected to the second gate terminal of the IGBT.

Semiconductor device, method for controlling semiconductor device, and control circuit for semiconductor device

Adverse effects can be hardly exerted on a current performance of an LDMOSFET to suppress the amount of carrier implantation from an anode layer of an LDMOS parasitic diode, and improve a reverse recovery withstand of the parasitic diode. The LDMOSFET includes a semiconductor substrate having a first semiconductor region formed of a feeding region of a first conductivity type at a position where a field oxide film is not present on a surface layer of a semiconductor region in which the field oxide film is selectively formed, and a second semiconductor region formed of a well region of a second conductivity type which is an opposite conductivity type, and feeding regions of the first conductivity type and the second conductivity type formed on an upper layer of the well region, and a gate electrode that faces the well region through a gate oxide film. The feeding region of the first semiconductor region is formed at a distance from the field oxide film near an end portion remote from the gate electrode, and desirably the feeding region is intermittently formed at intervals in the longitudinal direction.

Semiconductor device

A high voltage ESD protective diode having high avalanche withstand capability and capable of being formed by using manufacturing steps identical with those for a high voltage transistor to be protected, the device having a structure in which a gate oxide film is formed over a substrate surface at a PN junction formed of an N type low concentration semiconductor substrate constituting a cathode region and a P type low concentration diffusion region constituting an anode region, and a gate electrode which is disposed overriding the gate oxide film and a field oxide film is connected electrically by way of a gate plug with an anode electrode, whereby an electric field at the PN junction is moderated upon avalanche breakdown to obtain a high avalanche withstand capability. Further, the withstand voltage can be adjusted by changing the length of the field oxide film.

Method of manufacturing semiconductor device having high voltage ESD protective diode

The cell size is reduced and device reliability is improved for a semiconductor device including plural transistors making up a multi-channel output circuit. In a multi-channel circuit configuration, a group of transistors having a common function of plural channels are surrounded by a common trench for insulated isolation from another group of transistors having another function. The collectors of mutually adjacent transistors on the high side are commonly connected to a VH power supply, whereas the emitters of mutually adjacent transistors on the low side are commonly connected to a GND power supply.

Growing community of inventors

Tokyo, Japan

Tomoyuki Miyoshi