Kabushiki Kaisha Toshiba

Toshiba Electronic Devices & Storage Corporation

Tomoyuki Maekawa

Koji Maruyama

Toshiaki Sato

Kazuo Konishi

Shimpei Yoshioka

Katsutoshi Moriyama

Yusuke Ikeda

According to one embodiment, a circuit includes: a core circuit including first and second scan layers; and a test control circuit that controls a scan test on the first and second scan layers. The test control circuit supplies a first test data and a first shift clock to the first scan layer and then sets the first scan layer to a waiting state, supplies a second test data and a second shift clock to the second scan layer during a period in which the first scan layer is in the waiting state, sets the second scan layer to a waiting state after supplying the second test data and the second shift clock to the second scan layer, and supplies a first launch clock and a first capture clock to the first scan layer after setting the second scan layer to the waiting state.

Semiconductor integrated circuit and test method for semiconductor integrated circuit

A semiconductor device according to an embodiment includes a plurality of scan chains each including a retention flip-flop, and a control section configured to perform restoration of data saved in a retention section of each retention flip-flop by reading the data from the retention section and after the data restoration, perform diagnosis of the retention flip-flops by performing comparison to determine whether or not an expected value of an output data string obtained as a result of a scan shift in the plurality of scan chains before the save and a value of an output data string obtained as a result of a scan shift of data in the plurality of scan chains after the restoration.

Semiconductor integrated circuit and semiconductor integrated circuit diagnosis method

An optical disk recording device that detects a shift of the recording position with respect to an optical disk, has a pre-pit distribution detecting circuit that detects the distribution of pre-pits for a plurality of wobbles based on binarized pre-pit signals obtained by binarizing pre-pit signals corresponding to pre-pits on said optical disk and a wobble counter value obtained by counting said binarized pre-pit signals in synchronization with a locked wobble, which is a wobble signal having a period corresponding to a wobble on said optical disk and fixed in phase; and a wobble slip determining circuit that compares the distribution of said pre-pits detected by said pre-pit distribution detecting circuit and a reference pre-pit distribution corresponding to a desired recording position, thereby determining the shift amount of the recording position with respect to said desired recording position for each wobble.

Optical disk recording device which detects pre-pit distribution and shifts recording position accordingly

An ADIP decoder for decoding address in pre-groove (ADIP) of a wobble of an optical disc, has: a band pass filter that filters a wobble signal having a period corresponding to the wobble; a wobble PLL circuit that divides a frequency of a phase-locked clock signal in response to an input of the filtered wobble signal, and outputs a locked wobble signal; a timing generating circuit that generates a sampling timing signal based on the clock signal; an analog to digital converter that converts the filtered wobble signal into a digital signal in synchronization with the sampling timing signal; and an ADIP decoding circuit that counts a clock of the locked wobble signal with a counter, holds an address and one of a minimum amplitude value and a maximum amplitude value of the digital signal for each counter period, the address corresponding to a wobble clock count value where the digital signal has one of the minimum amplitude value and the maximum amplitude value, and that decodes the ADIP based on a distribution of the held address.

Optical disc apparatus and ADIP decoder

An error correction device for an optical disk reproduction unit for reproducing recorded information from an optical disk recorded with a code row data added with an error code in the same direction as a sequence of recorded information in the recording portion of the optical disk, and recorded guide information recorded in an inerasable state as a guide for recording the code row data before the code row data is recorded, wherein a prepit decoder as a first position detection portion is configured to detect a physical configurational singular point in the recorded guide information as a first position, a second position generating portion is configured to generate a second position replacing the first position detected by the prepit decoder with the code row data position, and an error correction circuit is configured to erase-correct error in the code row data using the second position.

Error correction device of optical disk unit

This invention provides a memory card device using an EEPROM as a semiconductor memory. When a data write-in defective area is detected in the storage area of the EEPROM, a space area is retrieved from the storage area of the EEPROM as a relieving area and data to be written into the data write-in defective area is written into the relieving area. Then, when the relieving area becomes full and a data write-in defective area is detected in the storage area of the EEPROM, another space area is retrieved from the storage area of the EEPROM as a new relieving area and data to be written into the data write-in defective area is written into the new relieving area.

EEPROM memory card device having defect relieving means

A memory card apparatus has an EEPROM as a semiconductor memory. Each time data is written in the EEPROM, link data representing a recording location of the data is written and managed in a link table. The link table has a flag region with a flag which is set when data write in the EEPROM is requested and is reset when the link data has completely been written in the link table. In case of card removal during operation or power failure, the flag set in the flag region of the link table is not reset and remains. Thus, by checking the flag area of the link table, the occurrence of card removal during operation or power failure can be detected, and various countermeasures can be conducted. Thus, the correspondency between the recorded contents in the EEPROM and the contents in the link table can be maintained as much as possible.

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Fujisawa, Japan

Tomoyuki Maekawa