Panasonic Corporation

Matsushita Electric Industrial Co., Ltd.

Tomoyuki Kumamaru

Keiichi Kusumoto

Takashi Andoh

Tetsuji Gotoh

In order to suppress an instantaneous carrying current (surge current) and power supply noise caused by the instantaneous carrying current (the surge current), the power supply cutoff structure of a semiconductor integrated circuit device comprises a switching circuit for controlling a power supply to a controlled circuit. The switching circuit includes a plurality of transistors each having a different current capability. The transistors are sequentially provided with a certain regularity, including from a low current capability transistor up to a high current capability transistor.

Semiconductor integrated circuit device, communication device, information reproducing device, image display device, electronic device, electronic control device, and mobile body

A semiconductor integrated circuit comprising a data holding circuit sets the data holding circuit to a desired data state by first setting the power-supply voltage of the data holding circuit to be less than a specified voltage, and then setting the power-supply voltage of the data holding circuit to the specified voltage or greater, regardless of the data state that is stored beforehand in the data holding circuit.

Semiconductor integrated circuit having a latch circuit

In a static circuit or the like, upper and lower terminals are both set to a first power supply potential Vdd in the operating state of an inverter circuit. In the non-operating state, the power supply potential of the upper terminal is reduced to a second power supply potential Vdd (<<Vdd ). Provided that an input signal of the inverter circuit has a potential Vdd (H level), an output signal thereof must be held at the ground potential (L level) in the operating state. This requires that a conductance Gp of a PMOS transistor and a conductance Gn of a NMOS transistor satisfy the relation: Gp<Gn. Therefore, a well terminal (lower terminal) of the PMOS transistor is set to a potential higher than the power supply potential Vdd in order to maintain the relation: Gp<Gn. Accordingly, a signal determined by the circuit in the operating state can be held even in the non-operating state, and the power supply voltage is set to an extremely low potential in the non-operating state of the circuit.

Growing community of inventors

Osaka, Japan

Tomoyuki Kumamaru