Panasonic Corporation

Socionext Inc.

Tomoyuki Ishizu

Kyoji Yamashita

Katsuhiro Ootani

Daisaku Ikoma

Gaku Suzuki

Yasuyuki Sahara

Kyouji Yamashita

Akinari Kinoshita

In a semiconductor device having paired transistors, an imbalance in characteristics of the paired transistors is reduced or prevented while an increase in circuit area is reduced or prevented. First and second transistors have first and second regions having the same active region pattern, and third and fourth transistors have third and fourth regions having the same active region pattern. The active regions of the third and fourth transistors have a longer length in the channel length direction than that of the active regions of the first and second transistors. The third and fourth regions have a narrower width in the channel length direction than that of the first and second regions.

Semiconductor device layout reducing imbalance in characteristics of paired transistors

Semiconductor device layout reducing imbalance characteristics of paired transistors

The present disclosure provides a method of performing circuit simulation of electrical characteristics of a transistor formed on a semiconductor substrate using calculators, each of which includes a memory. A first calculator receives mask layout data and distance-dependent data indicating a distance from the target transistor. Then, a second calculator calculates an area ratio of a layout pattern of a predetermined mask from the received mask layout data, and calculates a parameter &#x3b1; based on the area ratio and the distance-dependent data. Then, the second calculator B calculates a change &#x394;P in the electrical characteristics of the transistor based on the parameter &#x3b1;. This configuration provides highly accurate circuit simulation of the electrical characteristics of the transistor, which depend on variations in temperature distribution of the semiconductor substrate during heat treatment due to the mask layout pattern around the transistor.

Circuit simulation method and semiconductor integrated circuit

A simulation model of BT instability of a transistor in a semiconductor integrated circuit, wherein a bias condition of at least one terminal among the drain terminal, the source terminal and the substrate terminal of the transistor is set up as an independent bias condition from other terminals; and then a model parameter of the transistor is changed in the set bias condition.

Simulation model of BT instability of transistor

An active region and an isolation region are formed in the surface of a silicon semiconductor substrate having a (100) crystal plane as a principal surface. A gate insulating film and a gate electrode are formed on the active region in this order. A stress control film is formed to cover part of the active region where the gate electrode is not formed, the isolation region, the top surface of the gate electrode and sidewalls. A pair of stress control regions are formed to sandwich the gate electrode in the gate width direction of the gate electrode. In the stress control regions, the stress control film is not formed, or alternatively, a stress control film thinner than the stress control film formed on the gate electrode is formed.

Semiconductor device and method for manufacturing the same for improving the performance of mis transistors

A circuit simulation apparatus has a means to acquire data regarding a transistor, a model parameter generation unit for generating a model parameter representing effects of stress upon the transistor active region caused by the isolation region, and a simulation execution unit for evaluating characteristics of the transistor using a simulation program associated with the model parameter. The model parameter includes a term regarding width of the transistor active region, a term regarding width of the peripheral active region, and a term regarding width between the transistor active region and the peripheral active region.

Growing community of inventors

Kyoto, Japan

Tomoyuki Ishizu