Hitachi, Ltd.

Renesas Technology Corp.

Renesas Electronics Corporation

Other

Hitachi Device Engineering Co., Ltd.

Tomoyuki Ishii

Kazuo Yano

Takeshi Sakata

Toshiyuki Mine

Koichi Seki

Taro Osabe

Takashi Kobayashi

Masakazu Aoki

Yoshinobu Nakagome

Takashi Hashimoto

Kan Takeuchi

Hideaki Kurata

Toshiaki Sano

Norifumi Kameshiro

Riichiro Takemura

Kazumasa Yanagisawa

Tatsuo Nakagawa

Kazunori Furusawa

Yoshihiro Ikeda

Bryan Atwood

Kiyoo Itoh

Yoshitaka Sasago

Akira Kotabe

Katsuro Sasaki

Masayoshi Ishibashi

Kiyoto Ito

Midori Kato

Suguru Tachibana

Toshinori Miyoshi

Yoshiharu Nagashima

Mineo Senda

An information processing system includes a storing unit that stores evaluation data in which a plurality of subjects are associated with a plurality of evaluation expressions respectively and evaluation expression relationship data indicating relationships between the evaluation expressions, a question generating unit that generates and outputs questions on the basis of the evaluation data and the evaluation expression relationship data, and a matching unit that outputs information relating to the subject included in the evaluation data on the basis of responses when the responses with respect to the questions are input.

Information processing system and information processing method

The present invention is a system for monitoring a health state of a subject. The system is provided with: a measuring unit that chronologically measures the position of the subject in a facility in which the subject resides or stays; and an information processing unit that determines a health state of the subject by determining whether a chronological change in the position of the subject satisfies a predetermined determination condition.

Monitoring system

A vital signal measurement system including a plurality of terminals aims to facilitate synchronization of each terminal with respect to other terminals. Each of the plurality of terminals () is provided with a first vital signal sensor () for measuring a vital signal, a first memory () for storing a first data which is based on the vital signal, and a first radio communication unit () for communicating with other terminals by radio. The first data is applied with a sequence number corresponding to the first data and the number indicates an order in which the first data is acquired. A first terminal () included in the plurality of terminals performs resetting of the sequence number triggered by the synchronous signal which is received by the first radio communication unit.

Vital signal measurement device, and vital sign signal measurement system

For providing a cheap semiconductor memory device with improving reliability by level of a cell, in the place of escaping from defects on memory cells electrically, through such as ECC, and further for providing a cell structure enabling scaling-down in the vertical direction with maintaining the reliability, in a semiconductor memory device, upon which high-speeded read-out operation is required, a charge storage region is constructed with particles made from a large number of semiconductor charge storage small regions, each being independent, thereby increasing the reliability by the cell level.

Semiconductor device

To achieve a stable reading operation in a memory cell having a gain-cell structure, a write transistor is configured, which has a source and a drain that are formed on the insulating layer, a channel formed on the insulating layer and between the source and the drain and made of a semiconductor, and a gate formed on an upper portion of the insulating layer and between the source and the drain and electrically insulated from the channel by a gate insulating film and controlling the potential of the channel. The channel electrically connects the source and the drain on the side surfaces of the source and the drain.

The invention provides a voltage applying structure having a reduced area penalty with respect to a data line. A wiring forming a global data line and a local data line formed in a p-type well region are connected via a select transistor. Two select lines are formed on a gate electrode of the select transistor. One select line is electrically connected to the gate electrode of the select transistor, however, the other select line is not connected to the select transistor. That is, an insulator film is formed between the select line and the gate electrode. As mentioned above, two select lines shorter than a gate length are provided on one select transistor. The select line is structured such as to be connected to the other select transistor.

Semiconductor memory device and manufacturing method of the same

In a two-transistor gain cell structure, a semiconductor memory device capable of stable reading without malfunction and having small-area memory cells is provided. In a two-transistor gain cell memory having a write transistor and a read transistor, a write word line, a read word line, a write bit line, and a read bit line are separately provided, and voltages to be applied are independently set. Furthermore, a memory cell is connected to the same read word line and write bit line as those of an adjacent memory cell.

Semiconductor memory device

A semiconductor device includes a sense amplifier and a decoder provided on a semiconductor substrate together with memory cells provided above the sense amplifier and the decoder. Each of the memory cells includes a channel region, in which current flows in a direction perpendicular to a surface of the semiconductor substrate, a charge accumulation region provided along the channel region, and an insulator film provided between the channel region and the charge accumulation region.

Semiconductor device having global and local data lines coupled to memory mats

A memory cell with a small surface area is fabricated by forming source lines and data lines above and below and by running the channels to face up and down. The local data lines for each vertically stacked memory cell are connected to a global data line by way of separate selection by a molecular oxide semiconductor, and use of a large surface area is avoided by making joint use of peripheral circuits such as global data lines and sensing amplifiers by performing read and write operations in a timed multiplex manner. Moreover, data lines in multi-layers and memory cells (floating electrode cell) which are non-destructive with respect to readout are utilized to allow placement of memory cells at all intersecting points of word lines and data lines while having a folded data line structure. An improved noise tolerance is attained by establishing a standard threshold voltage for identical dummy cells even in any of the read verify, write verify and erase verify operations. A register to temporarily hold write data in a memory cell during writing is also used as a register to hold a flag showing that writing has ended during write verify. Also, a circuit comprised of one nMOS transistor is utilized as a means to change values on the write-end flag.

After forming a source-drain material film on an insulator layer, an opening portion reaching the insulator layer is formed in the source-drain material film. Then, a channel having desired thickness and a gate insulator are sequentially formed on the insulator layer and the source-drain material film in the opening portion. Thereafter, a gate material film embedding the opening portion is formed on the gate insulator. Subsequently, a cap film is formed on the gate material film, thereby forming the gate made of the gate material film. Then, a mask layer is formed on the source-drain material film. Next, the source-drain material film not protected by the mask layer is removed while protecting the gate by the cap film, thereby leaving the source-drain material film on both sides of the gate. The source-drain material film on one side becomes the source and that on the other side becomes the drain.

Method for fabrication of semiconductor device

Disclosed is a non-volatile semiconductor memory device that uses a inversion layer provided on a semiconductor substrate as a data line. The memory device can reduce variation of characteristics among memory cells and can reduce bit cost. A plurality of assist gates are formed in the upper part of a p-type well through a gate oxide film. In the upper part of an interlayer insulator that covers those assist gates are formed word lines that are used as control electrodes. The width of those word lines is, for example, 0.1 &#x3bc;m, and each word line is separated from its adjacent word lines by a side wall spacer that is a silicon oxide film having a thickness of about 20 nm.

Semiconductor memory device and method for producing the same

Three-dimensional semiconductor memory device having a first and second charge accumulation region

Flash memory is rapidly decreasing in price. There is a demand for a new memory system that permits size reduction and suits multiple-value memory. A flash memory of AND type suitable for multiple-value memory with multiple-level threshold values can be made small in area if the inversion layer is utilized as the wiring; however, it suffers the disadvantage of greatly varying in writing characteristics from cell to cell. Another promising method of realizing multiple-value memory is to change the storage locations. This method, however, poses a problem with disturbance at the time of operation. The present invention provides one way to realize a semiconductor memory device with reduced cell-to-cell variation in writing characteristics. The semiconductor memory has a source region and a drain region, which are formed parallel to each other, and an assist electrode which is between and parallel to the source and drain regions without overlapping, so that it uses, at the time of writing, the assist electrode as the assist electrode for hot electrons to be injected at the source side and it uses, at the time of reading, the inversion layer formed under the assist electrode as the source region or the drain region.

Growing community of inventors

Hachioji, Japan

Tomoyuki Ishii