Panasonic Corporation

Tomoyuki Aihara

Toshikazu Suzuki

Yoshinobu Yamagami

Masanori Shirahama

Marefusa Kurumada

A semiconductor memory device includes a memory cell provided at an intersection of a word line and a bit line, a precharge circuit connected to the bit line, a column select circuit controlled in accordance with a write control signal, and a clamp circuit provided as a write circuit. The clamp circuit includes a transistor configured to control the potential of a selected bit line to a first potential (e.g., 0 V), and a variable capacitor configured to control the potential of the selected bit line to a second potential (e.g., a negative potential) which is lower than the first potential. The capacitance of the variable capacitor decreases when a power supply voltage is increased, whereby the amount of a decrease from the first potential to the second potential is reduced.

Growing community of inventors

Osaka, Japan

Tomoyuki Aihara