Nec Corporation

Technische Universitát Dresden

Tomoyoshi Kobori

Katsutoshi Seki

Yuzo Senda

Katsunori Tanaka

Gerhard P Fettweis

Kosuke Nishihara

Atsushi Hatabu

Steffen Kunze

Emil Matus

Soji Mori

A data processing system includes a plurality of calculation processors cascaded and a plurality of counters connected to the plurality of calculation processors, respectively. The plurality of calculation processors process a task in an order in which the plurality of calculation processors are cascaded. A count value of an individual one of the plurality of counters is incremented when a corresponding one of the calculation processors starts to process a task and is decremented when a calculation processor in a lowermost stage among the plurality of calculation processors ends the task.

Data processing system and data processing method

Provided is a processing apparatus, including: a plurality of processing unit; at least one or more data buffers that are connected between a first processing unit and a second processing unit and is able to store data output from the first processing unit and data input to the second processing unit; a command buffer that stores a task command specifying execution of a task to be executed in one or more specific processing units, the command buffer being able to output the task command to the processing unit; and a task control unit that is configured to control operational processing in the task, by controlling at least one of the data buffer and the command buffer, on the basis of the task command, task setting information representing the processing unit in which the task is executed, and information representing a state of operational processing in respective processing unit.

Controlling execution of tasks in a series of operational processing by identifying processing units based on task command, task setting information, state of operational processing

A computation device according to the present invention includes: a first data storage unit that stores operation target data; an operation processing unit that executes an operation by using data; a data permutation unit that selects indicated data among the operation target data stored in the first data storage unit and data operated by the operation processing unit, provides predetermined delay for data received a delay indication among the indicated data based on a parameter, does not delay data not received a delay indication, executes permutation of indicated data based on a parameter, and outputs data operated in the operation processing unit and operation result data of the operation processing unit; and second data storage unit that stores the operation result data output by the data permutation unit.

Computation device, computation method, and medium

In an array processing section, using data strings entered from input ports, a plurality of data processor elements execute predetermined operations while transferring data to each other, and output data strings of results of the operations from a plurality of output ports. A first data string converter converts data strings stored in a plurality of data storages of a data storage group into a placement suitable for the operations in the array processing section, and enters the converted data strings into the input ports of the array processing section. A second data string converter converts the data strings output from output ports of the array processing section into a placement to be stored in the plurality of data storages of the data storage group.

Converting a data placement between memory banks and an array processing section

To provide a DMA transfer apparatus and a DMA transfer method capable of reducing traffic on a bus between an external shared memory and DMA controller with less additional hardware to effectively use a memory. A pattern generation sectionis provided in a DMA controllerand generates data of a predetermined pattern, such as a zero matrix or unit matrix, in the DMA controller when data is transferred from an external shared memoryto an internal memory. Further, transfer data read out from the external shared memory is temporarily held in a queuing sectionfor queuing. At this time, switching between the transfer data from the queuing section and predetermined pattern data is made based on the number of the transfer data.

DMA transfer device and method

In a multicore type error correction processing system which can simultaneously cope with a plurality of error correction methods and a plurality of code lengths, an interconnect parthas a barrel shifter which extends across a plurality of error correction processing parts-An error correction process can be selectively performed by collectively using a group of the plurality of the error correction processing parts-or by individually using each of individual error correction processing parts-in response to interconnection configuration information. With this structure, the plurality of the error correction processing parts-are collectively used if computation resources are insufficient and an idling error correction processing part is assigned to another error correction process if computation resources are excessive.

Multicore type error correction processing system and error correction processing apparatus

A first compiler generates one or more object codes from a program code for a first processor included in an arithmetic processing system to which a plurality of processors are mutually connected. A first linker links the generated one or more object codes to generate an execution file for the first processor. A parameter information generation unit generates, based on the information acquired from the first linker, parameter information used in a second processor included in the arithmetic processing system. A second compiler refers to a program code and the parameter information for the second processor to generate one or more object codes. A second linker links the generated one or more object codes to generate an execution file for the second processor.

Programming system in multi-core environment, and method and program of the same

In address generation processors, the start and the end of the processing for address generation need to be controlled in addition to controlling the processing for base address generation. A timing control unit manages control for address conversion on a clock cycle basis. The difference between the processing speed in the address generation processors and the processing speed in the address conversion circuit is absorbed by buffers.

Apparatus and method for address generation for array processor and array processor

To provide a dynamic image receiving apparatus which receives dynamic image streams coded with inter-frame prediction such as MPEG from a plurality of channels, and collects the dynamic image streams containing intra-frame coded pictures from each channel in a short time. The dynamic image receiving apparatus includes: a time information accumulative processing device which accumulates code receiving time of the intra-frame coded picture of the dynamic image stream, and periodicity time information containing one of or both of presentation time information and decoding time information contained in the dynamic image stream for each dynamic image stream of the plurality of channels; code receiving time predicting devices which predict the code receiving time of the intra-frame coded pictures based on the periodicity time information; and a channel selection control device which controls channel selection of the dynamic image stream to be received based on the predicted code receiving time information.

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Tokyo, Japan

Tomoyoshi Kobori