Kioxia Corporation

Toshiba Memory Corporation

Tomoya Sanuki

Yasuhito Yoshimizu

Hideaki Aochi

Keisuke Nakatsuka

Toshio Fujisawa

Takashi Maeda

Susumu Hashimoto

Yoshihiro Ueda

Yasuaki Ootera

Shiho Nakamura

Tsuyoshi Kondo

Takuya Shimada

Shinji Miyano

Michael Arnaud Quinsat

Masaki Kado

Nobuyuki Umetsu

Yuichi Ito

Masayuki Miura

Hiroshi Maejima

Mie Matsuo

Tatsuro Hitomi

Kenichiro Yoshii

Arata Inoue

Shinichi Kanno

Yoshiaki Fukuzumi

Takashi Fukushima

Kazushige Kawasaki

Koichiro Shindo

Tetsuaki Utsumi

Yusuke Higashi

Go Shikata

Hideto Horii

Yoshihiro Ohba

Hitomi Tanaka

Fumitaka Arai

Takayuki Miyazaki

Masaki Kondo

Takeshi Ishihara

Masayoshi Tagami

Yoshiro Shimojo

Hiroki Tokuhira

Xu Li

Hideo Wada

Kazuhito Hayasaka

Hideko Mukaida

Yuta Aiba

Hiroyuki Dohmae

Daisuke Fujiwara

Hiroto Nakai

According to one embodiment, when a first case-mounted memory device that includes a first memory device is not connected to a slot of a host apparatus and is stored in a second stocker, the host apparatus causes a second transport device to transport the first case-mounted memory device to the slot, and to connect it thereto. When the first case-mounted memory device is not connected to the slot and is not stored in the second stocker, the host apparatus causes a first transport device to transport the first memory device from a first stocker to a mounter, causes the mounter to mount the first memory device in a case, and causes the second transport device to transport the first case-mounted memory device to the slot and to connect it thereto.

Storage system

According to one embodiment, the array chip includes a three-dimensionally disposed plurality of memory cells and a memory-side interconnection layer connected to the memory cells. The circuit chip includes a substrate, a control circuit provided on the substrate, and a circuit-side interconnection layer provided on the control circuit and connected to the control circuit. The circuit chip is stuck to the array chip with the circuit-side interconnection layer facing to the memory-side interconnection layer. The bonding metal is provided between the memory-side interconnection layer and the circuit-side interconnection layer. The bonding metal is bonded to the memory-side interconnection layer and the circuit-side interconnection layer.

Semiconductor memory device having a circuit chip bonded to a memory array chip and including a solid-state drive controller and a control circuit

According to one embodiment, a storage device includes a control apparatus and a stocker. The control apparatus writes data to or reads data from a storage medium that includes a plurality of non-volatile memory chips. The stocker stores a plurality of the storage media that are detached from the control apparatus. The control apparatus includes a first temperature control system. The first temperature control system raises temperature of the storage medium to a first temperature or higher. The stocker includes a second temperature control system. The second temperature control system cools the storage medium to a second temperature or lower. The second temperature is lower than the first temperature.

Storage device and control method

According to one embodiment, a semiconductor memory device includes a memory cell, a first voltage generator and a second voltage generator. The memory cell is provided above a substrate. The first voltage generator is provided between the substrate and the memory cell. The first voltage generator is configured to generate a first voltage to be supplied to the memory cell. The second voltage generator is provided between the substrate and the memory cell. The second voltage generator is configured to generate the first voltage and have a circuit configuration equivalent to the first voltage generator.

Semiconductor memory device

According to one embodiment, a controller includes a first interface, a second interface, a virtual register table, a memory management unit and a calculation processing unit. The first interface receives an I/O command from a host. The second interface transmits and receives first host data to and from a storage. The virtual register table has a virtual address specified by a page number assigned to a page in which data to be used to process a calculation instruction is stored and a page offset, and a data size of the data. The memory management unit stores, into a memory, the copy of the first host data, and updates the virtual register table. The calculation processing unit processes the calculation instruction by referring to the virtual register table.

Controller and control method

In one embodiment, a semiconductor device includes a first substrate including first and second regions on its surface, a first control circuit on the first substrate in the first region, a first memory cell array above the first control circuit in the first region and connected to the first control circuit, and a first pad above the first memory cell array in the first region and connected to the first control circuit. The device further includes a second control circuit on the first substrate in the second region, a second memory cell array above the second control circuit in the second region and connected to the second control circuit, a second pad above the second memory cell array in the second region and connected to the second control circuit, and a connection line above the first and second memory cell arrays and connecting the first and second pads.

Semiconductor device and method of manufacturing the same

According to one embodiment, a memory system includes a nonvolatile semiconductor storage device and a memory controller. The nonvolatile semiconductor storage device includes at least one memory device including a plurality of memory cells corresponding to a plurality of pages. The memory controller is configured to control the nonvolatile semiconductor storage device. The pages include a first page. The memory controller is configured to: read first data stored in the first page from the nonvolatile semiconductor storage device; correct a fail bit included in the read first data; generate first spare data including information on the fail bit corrected in the read first data; and store the first spare data in the nonvolatile semiconductor storage device.

Memory system

A method of processing a memory system that includes a substrate with a connector and a semiconductor memory chip connected to the connector is provided. The method includes detaching the semiconductor memory chip from the connector, performing an annealing process with respect to the semiconductor memory chip detached from the connector, and after the annealing process, attaching the semiconductor memory chip to the connector on the substrate.

Memory system and processing method of memory system

A semiconductor storage device includes a memory cell array and a control circuit. The memory cell array includes a plurality of memory strings, a plurality of word lines, each of which is connected to the memory strings, and a plurality of bit lines connected to the memory strings, respectively. The plurality of bit lines are grouped into a plurality of bit line groups. The control circuit is configured to receive a read command and first address information specifying one or more of the bit line groups. The control circuit is configured to, in response to the read command, read data selectively from each memory string connected to each bit line in the one or more bit line groups specified by the first address information, and output the read data.

Semiconductor storage device and system

According to one embodiment, a semiconductor device includes a first substrate and a logic circuit provided on the first substrate. The device further includes a memory cell provided above the logic circuit and a second substrate provided above the memory cell. The device further includes a bonding pad provided above the second substrate and electrically connected to the logic circuit. The device further includes a wiring that is provided above the second substrate, is electrically connected to the memory cell, and includes at least one of a data signal line, a control voltage line, and a power supply line.

A semiconductor memory device including: plural first conductive layers stacked on a substrate; plural second conductive layers each stacked between the first conductive layers; a pillar that extends in a stacking direction of the first and second conductive layers and forms plural memory cells at intersections of the first and second conductive layers in a region where first and second conductive layers are arranged; a first contact plug that extends in the stacking direction of the first and second conductive layers and is connected to the first conductive layers in the region where the first and second conductive layers are arranged; and a second contact plug that extends in the stacking direction of the first and second conductive layers and is connected to the second conductive layers in the region where the first conductive layers and second conductive layers are arranged.

Semiconductor memory device having contact plugs extend in the stacking direction of the plurality of the first and second conductive layers

A semiconductor memory device has a plastic package including an inductor, a first memory chip including a booster circuit that boosts a voltage from a first voltage to a second voltage using the inductor, and a second memory chip having a terminal supplied with the second voltage from the first memory chip.

A memory chip unit includes a pad electrode including first and second portions, and a memory cell array. A prober includes a probe card and a movement mechanism. The probe card includes a probe electrode to be in contact with the pad electrode, and a memory controller electrically coupled to the probe electrode and executes reading and writing on the memory cell array. The movement mechanism executes a first operation that brings the probe electrode into contact with the first portion and does not bring the probe electrode into contact with the second portion, and a second operation that does not bring the probe electrode into contact with the first portion and brings the probe electrode into contact with the second portion.

Storage system, memory chip unit, and wafer

A radiation detection device includes a non-volatile memory chip including a plurality of stacked memory cells, and a controller configured to detect gamma rays incident on the non-volatile memory chip during a gamma ray detection window according to a data inversion or a threshold voltage change of at least some of the memory cells in the non-volatile memory chip during the gamma ray detection window.

Radiation detection device, semiconductor memory device and radiation detection method

Semiconductor memory device including integrated control circuit and solid-state drive controller

Growing community of inventors

Suzuka Mie, Japan

Tomoya Sanuki