Kabushiki Kaisha Toshiba

Toshiba Microelectronics Corporation

Tomoya Osaki

Naohito Morozumi

Masaru Kito

Toshiyuki Kondo

Toru Matsuda

Katsumasa Hayashi

Seishi Irie

A semiconductor memory device includes a memory cell array layer which includes a first wiring line, a memory cell stacked on the first wiring line, and a second wiring line formed on the memory cell so as to intersect the first wiring line, wherein a step is formed in the first wiring line so that the height of an upper surface of the first wiring line in the memory cell array region where the memory cell array is formed is higher than the height in a peripheral region around the memory cell array region.

Semiconductor memory device having a wiring in which a step is provided

Semiconductor memory device having a low resistance wiring line and method of manufacturing the same

A semiconductor memory device includes a substrate, a conductive layer provided on a major surface of the substrate, a stacked body, a memory film, and a channel body. The stacked body includes multiple insulating layers alternately stacked with multiple electrode layers on the conductive layer. The memory film includes a charge storage film provided on side walls of holes made to pierce the stacked body. The channel body includes a pair of columnar portions and a linking portion. The pair of columnar portions is provided on an inner side of the memory film inside the holes. The linking portion is provided inside the conductive layer to link lower ends of the pair of columnar portions. The electrode layers are tilted with respect to the major surface of the substrate. The columnar portions of the channel body and the memory film pierce the tilted portion of the electrode layers.

Semiconductor memory device and method for manufacturing same

A semiconductor memory device includes a cell array having matrix-like arrayed plural SRAMs on a semiconductor substrate having an N-well and P-well. The N-well and the P-well are isolated from each other with an isolation region each having a shallow trench structure. Each memory cell includes two CMOS inverter circuits having input and output nodes making a cross-coupled connection. First and second capacitors are connected between each gate node of two CMOS inverter circuits and the N-well and/or N-well.

Semiconductor memory device having a shallow trench isolation structure

Growing community of inventors

Yokkaichi, Japan

Tomoya Osaki