Mitsubishi Denki Kabushiki Kaisha

Renesas Technology Corp.

Mitsubishi Electric Corporation

Tomoya Kawagoe

Tsukasa Ooishi

Hideto Hidaka

Mikio Asakura

Jun Ohtani

Katsumi Dosaka

Takeshi Hamamoto

Kohei Mori

Mitsutaka Niiro

Jun Otani

Akihisa Oishi

To provide a positioning apparatus which can reduce the error of the positioning information of the positioning satellite, by using either appropriate one of the positioning reinforcement information by the ground channel or the positioning reinforcement information by the satellite channel, according to execution state of the automatic driving. A positioning apparatus receives positioning information from positioning satellites; calculates a first own position based on the positioning information and the positioning reinforcement information of the ground base station; calculates a second own position based on the positioning information and the positioning reinforcement information of the satellite; determines either the first own position or the second own position to be used, based on whether or not the driving mode is the automatic driving mode; and outputs the first own position or the second own position determined to be used, as a final own position.

Positioning apparatus

Provided are an automatic driving control system and an automatic driving control method that are capable of clearing away suspicion of a foul by exchanging a 'hand' for determining priority of passage by a fair method that allows no foul when automatically driven vehicles face each other on a road. When the automatically driven vehicles face each other on the road, the 'hand' for determining the priority of passage is exchanged by performing transmission/reception two times by use of a composite number of prime numbers each having a large number of digits.

Automatic driving control system and automatic driving control method

A nonvolatile semiconductor memory device includes a free layer having first and second magnetic layers magnetized oppositely to each other, and also having a first nonmagnetic layer formed between the first and second magnetic layers, a first fixed layer having a fixed magnetization direction, a second nonmagnetic layer formed between the second magnetic layer and the first fixed layer, a first drive circuit passing a write current through a first write current line in a data write operation, and thereby generating a data write magnetic field acting on magnetization of the free layer, and a second drive circuit passing a spin injection current between the first magnetic layer and the first fixed layer in a data write operation, and thereby exerting a force in the same direction as or in the direction opposite to the magnetization direction of the first fixed layer on the magnetization of the free layer.

Nonvolatile semiconductor memory device performing data writing in a toggle manner

In an exclusive OR circuit (XOR gate) constituting an ECC circuit, the drivability of P channel MOS transistors is set larger than the drivability of N channel MOS transistors. Accordingly, the speed of the logic level of an output node being set to an H level from an L level identified as a reset state is increased than the case where the drivability is set equal. Thus, the time required to output a syndrome from a plurality of stages of XOR gates can be reduced to allow execution of error correction processing at high speed.

Semiconductor device improving error correction processing rate

At the time of burn-in test, substrate voltages of transistors in a sense amplifier are switched by a PMOS substrate voltage generating portion and an NMOS substrate voltage generating portion. Specifically, the substrate voltage of a P channel MOS transistor is increased during the test than in a normal operation, whereas the substrate voltage of an N channel MOS transistor is decreased during the test than in the normal operation. Consequently, the threshold voltages of the P channel and N channel MOS transistors can be increased upon the test. Leakage currents in the turned-off states can be reduced, and thus, power consumption during the burn-in test can be decreased.

Semiconductor memory device reduced in power consumption during burn-in test

Following data writing into a memory cell array according to an internal address signal, the data read out from each memory cell is compared with expected value data in a readout operation. An associated memory cell array and a test block are provided corresponding to each sub memory cell array. Each test block includes a replacement determination unit for respective combinations of a sequence to replace a memory cell row and a memory cell column in order. Each replacement determination unit writes a defective address only when a defective memory cell having an address differing from the row and column addresses of a defective memory cell already stored is found.

Semiconductor integrated circuit device including semiconductor memory with tester circuit capable of analyzing redundancy repair

A tester is connected to a signal output terminal provided in a DRAM chip, and a frequency of a clock signal output from an internal timer is monitored. The frequency of the clock signal is varied by changing the combination of 3 bit signals, so as to obtain signals by which the frequency closest to the set value is obtained. A fuse in the internal timer is disconnected to set the frequency of the clock signal so as to obtain the same state as in the case where that signal is applied. The internal timer includes an oscillator formed of a plurality of inverters connected in ring shape and a variable capacitance circuit for each inverter. Each variable capacitance circuit includes a plurality of sets of transfer gates, fuses and capacitors connected between the output node of the corresponding inverter and a prescribed potential line.

Ring oscillator having variable capacitance circuits for frequency adjustment

A memory cell array is divided into a first and second sub-memory cell arrays. A built-in self-testing circuit is provided with an address replacement determining circuit which is installed in each of the first and second sub-memory cell arrays, and which, assuming that a selection of a memory cell from the first and second sub-memory cell arrays and a replacement thereof to a preliminary memory cell can be carried out mutually in an independent manner, makes a determination as to which preliminary memory cell is used for replacement, and outputs the result of determination.

Semiconductor integrated circuit device provided with a self-testing circuit for carrying out an analysis for repair by using a redundant memory cell

Built-in self-test circuit and built-in redundancy analysis circuit are provided commonly to plural DRAM cores. Built-in redundancy analysis circuit determines a defective address to be replaced with one of plural spare memory cell rows and plural spare memory cell columns according to an address signal and a detection result of a defective memory cell from built-in self-test circuit. Built-in redundancy analysis circuit controls an effective service area of an address storage circuit into which a defective address is stored according to a capacity of a DRAM core to be tested.

Semiconductor integrated circuit device capable of self-analyzing redundancy replacement adapting to capacities of plural memory circuits integrated therein

After writing data into a memory cell array according to an internal address signal, data read out from each memory cell is compared with expected value data in a read out operation. When there are two spare rows and two spare columns provided, a replacement determination unit is provided for each of the sixth types of sequences sequentially replacing a memory cell row and a memory cell column. A defective address is written into four sets of storage cell trains provided corresponding to each replacement determination unit only when a defective memory cell is detected having an address differing from at least one of a row address and column address of a defective memory cell that is already stored.

Semiconductor device including tester circuit suppressible of circuit scale increase and testing device of semiconductor device

A select signal generating circuit S,issues two pulse signals onto select signal line CEL under the control by chip,of a master chip. The select signal line CEL has a folded form. The D-flip-flop detects the fact that the second pulse signal issued from the select signal generating circuit S,arrives at the position of the corresponding slave chip when a first pulse signal issued from the select signal generating circuit S,and returning from the folded point of the select signal line CEL arrives at the position of the same slave chip, whereby selection of the chip is performed.

Slave circuit select device which can individually select a plurality of slave circuits with one data bus

A tester is connected to a signal output terminal provided in a DRAM chip, and a frequency of a clock signal output from an internal timer is monitored. The frequency of the clock signal is varied by changing the combination of 3 bit signals, so as to obtain signals by which the frequency closest to the set value is obtained. A fuse in the internal timer is disconnected to set the frequency of the clock signal so as to obtain the same state as in the case where that signal is applied.

Semiconductor device and testing apparatus thereof

A nonvolatile semiconductor memory cell includes four ferroelectric capacitors and six N channel MOS transistors. When data is to be written or read to or from a certain ferroelectric capacitor, corresponding two word lines are activated.

Nonvolatile semiconductor memory device reduced in occupy area of memory

A semiconductor memory device includes a plurality of memory cells, a plurality of address detecting circuits capable of registering a defective address indicating a defective memory cell out of the plurality of memory cells for detecting whether an external address matches the defective address or not and each corresponding to 1 bit of the external address or complementary 1 bit thereof, and first and second terminals. Each of the address detecting circuits includes first and second capacitors each having a floating electrode formed of the same layer as a cell plate electrode of a memory cell, a fixed electrode formed of the same layer as a storage node electrode of the memory cell, and a dielectric layer formed of the same layer as a dielectric layer of the memory cell and formed between the floating electrode and the fixed electrode. If 2.times.Vcc is applied to the first terminal and 2.times.Vcc+.delta. is applied to the second terminal, charges are charged in the first and the second capacitors. If ultraviolet rays are directed to the second capacitor, charges are left in respective floating electrodes of the first and the second capacitors, whereby the defective address can be registered in a non-volatile manner. Accordingly, the semiconductor memory device can be manufactured without increase in the number of manufacturing steps, and can replace a defective memory cell with a spare memory cell.

Growing community of inventors

Hyogo, Japan

Tomoya Kawagoe