J-devices Corporation

Tomoshige Chikai

Hiroaki Matsubara

Shingo Nakamura

Shotaro Sakumoto

Yoshikazu Kumagaya

Sumikazu Hosoyamada

Takeshi Miyakoshi

Toshihiro Iwasaki

Shinji Watanabe

Kiminori Ishido

Hirokazu Honda

Michiaki Tamakawa

Takashi Nakamura

Hiroshi Inoue

Osamu Yamagata

Hiroshi Demachi

Tomoko Takahashi

Naoki Hayashi

Akio Katsumata

Shigenori Sawachi

Satoru Itakura

Hisakazu Marutani

Koichiro Niwa

Masahiko Hori

Yasunari Iwami

Shingo Mitsugi

Chunghao Chen

A semiconductor device includes a lead frame; a circuit board located on the lead frame; a power device that includes a switching element and is mounted on the circuit board via a bump located between the power device and the circuit board; and a heat releasing member connected to the power device. The circuit board may be a multi-layer wiring board. The circuit board may include a capacitor element, a resistor element, an inductor element, a diode element and a switching element.

Semiconductor device

A stacked semiconductor package in an embodiment includes a first semiconductor package including a first circuit board and a first semiconductor element mounted on the first circuit board; and a second semiconductor package including a second circuit board and a second semiconductor element mounted on the second circuit board, the second semiconductor package being stacked on the first semiconductor package. The first semiconductor package further includes a sealing resin sealing the first semiconductor element; a conductive layer located in contact with the sealing resin; and a thermal via connected to the conductive layer and located on the first circuit board.

Semiconductor package

An interconnect structure in which the current capacity of an interconnect pattern involving a large amount of current is increased without preventing the miniaturization of signal lines and increasing the film thickness. The interconnect structure includes a resin layer; and interconnects formed on the resin layer, wherein the resin layer has a plurality of parallel grooves in an area in which the interconnects are formed, and the interconnects are formed of a plating film created on a resin layer front surface in the area, in which the interconnects are formed, and on inner wall surfaces of the plurality of grooves.

Interconnect structure, printed circuit board, semiconductor device, and manufacturing method for interconnect structure

A stacked semiconductor package includes a first semiconductor package including a first circuit board and a first semiconductor device mounted on the first circuit board; a second semiconductor package including a second circuit board and a second semiconductor device mounted on the second circuit board, the second semiconductor package being stacked on the first semiconductor package; and a heat transfer member provided on the first semiconductor device and a part of the first circuit board, the part being around the first semiconductor device.

A magnetic shielding package of a non-volatile magnetic memory element, including: a soft magnetic material support plate; a first insulating material layerformed on the support plate; a non-volatile magnetic memory elementfixed on the first insulating material layer; a second insulating material layerthat encapsulates the memory element and the periphery thereof; in the second insulating material layer, a wiring layer, a soft magnetic layerorand a conductive portionconnecting an electrode of the circuit surface of the memory element and the wiring layer; and a magnetic shield partcontaining a soft magnetic material arranged like a wall at a distance from a side surface of the memory element so as to surround the memory element side surface partially or entirely, the magnetic shield part being magnetically connected to the soft magnetic layer.

Magnetic shielding package of non-volatile magnetic memory element

A manufacturing method for a semiconductor device of the present invention includes: preparing a semiconductor wafer including an electrode formed therein; electrically connecting a first semiconductor element formed in a semiconductor chip and the electrode formed in the semiconductor wafer; filling a gap between the semiconductor wafer and the semiconductor chip with a first insulating resin layer; forming a second insulating resin layer on the semiconductor wafer; grinding the second insulating resin layer and the semiconductor chip until a thickness of the semiconductor chip reaches a predetermined thickness; forming a first insulating layer on the second insulating resin layer and the semiconductor chip; forming a line on the first insulating layer connected with a conductive material filled an opening in the first insulating layer and the second insulating resin layer to expose the electrode; and grinding the semiconductor wafer until a thickness of the semiconductor wafer reaches a predetermined thickness.

Manufacturing method for semiconductor device

A semiconductor package includes a support substrate arranged with a first aperture reaching a semiconductor device on a rear side, the semiconductor device is bonded via an adhesive to a surface of the support substrate, an insulating layer covering the semiconductor device, and wiring for connecting the semiconductor device and an external terminal through the insulating layer. The adhesive may form a part of the first aperture. In addition, a heat dissipation part may be arranged in the first aperture and a metal material may be filled in the first aperture.

Heat sink in the aperture of substrate

A semiconductor device containing: a semiconductor element; a support substrate; an insulating material layer for sealing the semiconductor element and a periphery thereof; a metal thin film wiring layer provided in the insulating material layer, with a part thereof being exposed on an external surface; and metal vias provided in the insulating material layer and electrically connected to the metal thin film wiring layer. The semiconductor element is provided in a plurality of units and the respective semiconductor elements are stacked via an insulating material such that a circuit surface of each semiconductor element faces the metal thin film wiring layer, and electrode pads of each semiconductor element are exposed without being hidden by the semiconductor element stacked thereabove.

Semiconductor device and manufacturing method thereof

A semiconductor device comprising a support plate, a semiconductor element mounted on the support plate and including a circuit element surface having a plurality of first electrodes, a first insulation layer covering the circuit element surface of the semiconductor element, and including a plurality of first apertures exposing the plurality of first electrodes, a second insulation layer covering an upper part of the support plate and side parts of the semiconductor element, and wirings formed on an upper part of the first insulation layer and on an upper part of the second insulation layer, and electrically connected to the corresponding first electrodes.

Growing community of inventors

Kanagawa, Japan

Tomoshige Chikai