Kawasaki Microelectronics, Inc.

Tomoo Tsuda

Yuki Narita

Masahiro Konishi

Ryuichi Hata

The invention provides a content addressable memory device having the capability of functioning as a content addressable memory device with a reduced memory capacity even when the device includes a large number of failed words in some memory blocks. To achieve the above object, the content addressable memory device according to the present invention includes a memory part including a plurality of memory blocks which can be controlled independently of each other, a failed memory block information memory for, when there is a failed memory block, storing address information associated with the failed memory block and outputting a signal indicating the failed memory block, and an encoder for, in accordance with the signal and an address input from the outside, outputting a memory block selection signal to the respective memory blocks to enable a memory block other than the failed memory block without enabling the failed memory block.

Content addressable memory device capable of reducing memory capacity

A content addressable memory device includes a plurality of memory banks. A faulty memory bank, if present, is excluded from the memory capacity thereof so that the content addressable memory device is used with the memory capacity thereof reduced. The content addressable memory device includes a plurality of banks, each bank including a plurality of words for storing data, an excluded bank information memory for storing information concerning an excluded bank, a mapping circuit for mapping an enable signal designating a bank to a bank other than the excluded bank, based on the excluded bank information, and a demapping circuit for mapping, to bank addresses including the address of the excluded bank, a hit signal representing that a word storing data corresponding to input search data is present in its own bank.

Content addressable memory device for compensating faults

A ternary content addressable memory device is disclosed which writes data into a data cell and writes mask data into a mask data cell in a ternary CAM cell unit by a single write cycle when the ternary content addressable memory device is used as a binary content addressable memory device. The content addressable memory device includes at least the ternary content addressable memory cell unit which stores ternary data representing three states of &ldquo;0&rdquo;, &ldquo;1&rdquo;, and &ldquo;don't care&rdquo;. The ternary content addressable memory cell unit include the data cell for storing binary data of &ldquo;0&rdquo; and &ldquo;1&rdquo;, and the mask cell for storing mask data for masking the binary data from a searching operation. The content addressable memory device includes a write circuit which writes the binary data into the data cell while writing the mask data in an unmask state into the mask cell at the same time, when the binary data is written into the ternary content addressable memory cell unit.

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Mihama-ku, Japan

Tomoo Tsuda