Hitachi, Ltd.

Tomoo Murata

Takeo Yamashita

Mitsugu Kusunoki

Shinobu Yabuki

Atsushi Okumura

Kenichiro Yamaguchi

A duty compensation circuit including a duty detection circuit, a duty adjustment signal generator for generating a control signal from a detected duty, and a duty adjustment circuit, in which the duty detection circuit executes sampling of a clock at sampling timing obtained by causing the clock to be delayed by a variable delay circuit, thereby detecting a duty. Thereby, duty compensation is enabled without preparing a clock higher in operating speed than a clock before compensation.

Duty compensation circuit

When an optical signal that is a wide dynamic range and different in level depending on burst signals is input as in a GPON system, a preamplifier can stably control the gain within a short preamble. The gain changeover of the preamplifier is controlled by the aid of timing information that is extracted from a data signal as data count number, to change over the gain at a high speed and with high precision. A level detector, a preamble recovery, a counter, and a control circuit are disposed within the preamplifier in addition to a TIA main body. In order to suppress the band deterioration or the phase margin reduction which are attributable to the gain changeover, there is provided a bias terminal for conducting a current injection and a current drawing with respect to the signal amplification transistor of the TIA main body.

Preamplifier and optical receiving apparatus using the same

Operating speed as well as output accuracy of a D-A converter is enhanced. With a semiconductor device including unit current sources, and unit current source switches, plural current source elements constituting each of the unit current sources are disposed so as to be evenly dispersed, thereby reducing errors of the current source element, dependent on distance while the unit current source switches are concentratedly disposed in a small region, thereby mitigating delay in operation, attributable to parasitic capacitance. In addition, with the semiconductor device including R2R resistance ladders, the R2R resistance ladder is provided on the positive and the negative of each of the unit current source switches, and the respective R2R resistance ladders are shorted with each other at respective nodes on a unit current source switch-by-unit current source switch basis, are rendered identical in length, thereby cancelling out a nonlinearity error attributable to wiring parasitic resistance.

Semiconductor device

In a method of manufacturing a semiconductor device having a first wiring extending in a first direction and a second wiring connected to the first wiring through a connection and extending in a second direction orthogonal to the first direction, the second wiring having a surplus portion projecting from the connection in a direction opposite to the second direction, the first and second wirings are arranged such that a center of the connection is offset in the second direction from a center of the first wiring, and a projecting portion of the first wiring is disposed under the connection.

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Fussa, Japan

Tomoo Murata