Matsushita Electric Industrial Co., Ltd.

Panasonic Intellectual Property Corporation of America

Panasonic Corporation

Tomoo Kimura

Ikuo Fuchigami

Tomonori Kataoka

Youichi Nishida

Yoichi Nishida

Ryuji Fuchikami

Ken Kawai

Junji Michiyama

Satoshi Kohtaka

Jyunji Michiyama

Kenji Shimizu

Akihiro Miyazaki

Takeshi Shimamoto

Hiroto Tomita

Shinsuke Ogata

Ryouta Hata

Kenichi Ishida

Keisuke Hayata

Yasuhiro Ishiyama

Tomoyuki Inomoto

Satoshi Koutaka

A stylus detecting device detects a pointed position which is a position pointed to by a stylus, and includes a first camera; a second camera; and a control unit including an axis detecting unit that detects a three-dimensional position and attitude of an axis of the stylus by using two images captured respectively by the first and second cameras, and a pointed position detecting unit that calculates as the pointed position a point of intersection between a straight line indicated by the axis of the stylus whose three-dimensional position and attitude have been detected by the axis detecting unit and a target plane having a predetermined positional relationship with respect to the first and second cameras.

Stylus detecting device and stylus detecting method

The picture quality of captured images can be improved with the degradation of clearness of image-captured object boundaries suppressed. An image processing apparatus () comprises: an image/distance acquiring unit () that acquires corresponding pixel pairs between left-eye and right-eye images, its depth information and its matching scores; a weight information calculating unit () that determines, for each of the pixel pairs, a weight of each of the pixels in a certain area including, as pixels of interest, the pixel pair on the basis of the depth information and the matching scores; and a pixel value superimposing unit () that applies, for each of the pixel pairs, the weight to the pixel values in the aforementioned certain area, thereby performing a smoothing process in at least one of the two images and that superimposes the two images using the values obtained by the smoothing process.

Image processing apparatus and image processing method

An imaging device includes a frame rate conversion unit synthesizing images captured at a second frame rate higher than a first frame rate to convert the images into a synthesized image having the first frame and a motion estimation unit performing motion estimation between consecutive frames of the images captured at the second frame. The imaging device also includes a motion vector synthesis unit synthesizing motion vectors having the second frame rate, to generate a synthesized motion vector of a target macroblock in the synthesized image, a motion blur amount determination unit counting, in an area surrounding the target macroblock, the number of macroblocks having the same synthesized motion vector as the target macroblock and comparing a value derived from the number of counted macroblocks with a threshold value, and a motion vector selection unit selecting the synthesized motion vector when the derived value determined to exceed the threshold value.

Imaging device for motion vector estimation using images captured at a high frame rate with blur detection and method and integrated circuit performing the same

An image control device, which achieves energy saving effects without degradation of an image to be displayed, even if image data includes a fault, is configured to decode received image data into an image, generate display information based on the received image data, and output a decoded image and display information. The image control device receives image data, detects errors from the image data. For each error detected, the image control device specifies a fault image region containing an error from an entire image region of the image data, and inhibits use of the fault image region for generating display information that defines an image display condition according to which the display device performs the image display.

Image control device and image display system for generating an image to be displayed from received imaged data, generating display information based on the received image data and outputting the image and the display information to a display

A frame brightness detecting unitdetects a frame brightness value of each of a plurality of image frames. A flicker spectrum detecting unitdetects, from the frame brightness values of 512 frames, spectrum values at frequencies, such as 100 Hz, 200 Hz, and 300 Hz. A brightness estimating unitestimates a brightens value of a light source from the spectrum values. An encoding unituses a reciprocal of the estimated brightens value to determine a reference frame. The encoding unitalso uses the reciprocal in an evaluation function for motion vector estimation. The image frame is encoded using the motion vector.

Imaging device, integrated circuit, and imaging method for encoding image frames based on detected flicker of a light source

A semiconductor integrated circuit having a circuit block including a MOS transistor that includes a bias input terminal, a source, and a substrate, in which the bias voltage is applied to the MOS transistor at a position of at least one of the source and the substrate through the bias input terminal, a setting unit operable to set up applying timing and releasing timing at which the bias voltage is applied to and released from the MOS transistor, and a bias voltage-applying unit operable to apply the bias voltage to the MOS transistor at the applying timing and the releasing timing. In the semiconductor integrated circuit, the setting unit sets up, as the releasing timing, timing prior to activation timing by a predetermined time period. An operation-requesting signal, to be sent out to the circuit block by the setting unit, is activated at the moment of the activation timing.

Semiconductor integrated circuit

A dividing flip-flop FFis inserted in a cluster C of which the cluster length exceeds a predetermined cluster length. The flip-flop inserted cluster C is re-clustered, generating subdivided clusters Cand C. Therefore, the degree of freedom is increased in allocating clusters to a variable logic element such as an FPGA in a logical emulation device.

Logic circuit optimizing method, logic circuit optimizing device and logic circuit composing device

In the circuit operation verifying method, initialization includes inputting circuit diagram data (a net list), specification information on respective circuit elements, and input data representing waveforms with time of voltages or currents used for operation simulation, and storing the circuit diagram data to memory. Operation of a semiconductor circuit to be verified is simulated using the circuit diagram data and the input data, and momentary voltage/current values at input terminals and the like of the circuit elements are stored in the memory. During the operation simulation, whether or not the circuit elements satisfy their voltage/current specifications and time specifications are concurrently verified based on the voltage/current values stored in the memory.

Circuit operation verifying method and apparatus

A current sense amplifier circuit is provided with a reference current generator for generating a reference current according to the characteristics of a memory cell, and a current comparator, and the current comparator compares the memory cell current with the reference current. Thereby, the range of the operating power supply voltage is increased. Further, a current sense amplifier circuit is provided with plural sets of reference current generators and current comparators, and the reference current generators generate reference currents of different amounts corresponding to plural states the memory cell can take, and the current comparators compare the respective reference currents with the memory cell current. Therefore, it is possible to detect the current in the memory cell that is set in multiple states.

Current sense amplifier circuit

The present invention provides a semiconductor memory which can reduce the area of a circuit for replacing defective memory cells with redundant memory cells as well as reduce the time for writing defect information. The semiconductor memory of the present invention comprises a memory cell array,comprising (n&plus;1) (n is a positive integer) word lines, a register unit,holding an encoded defect address for specifying a defective word line, a defect address decoder,for decoding the defect address from the register unit,to specify the defective word line, selection means S,&tilde;Sn for selecting, for the i-th (1&lE;i&lE;n) output signal line of a row decoder,, one of the i-th and i&plus;1-th word lines and connecting the selected word line to the i-th output signal line, and control means C,&tilde;Cn each controlling corresponding one of the selection means S,&tilde;Sn on the basis of an output of the defect address decoder,so as to select, for the output signal line of the row decoder,, one of the word lines except the defective word line in accordance with the arrangement order.

Semiconductor memory having reduced time for writing defective information

A semiconductor integrated circuit includes a booster for boosting a power supply voltage, and outputting the boosted voltage; an output circuit being supplied with the boosted voltage, and generating an output voltage from the boosted voltage; a reference voltage generator being supplied with the power supply voltage, and generating a reference voltage from the power supply voltage; a voltage divider being supplied with the output voltage from the output circuit, and dividing the output voltage with a predetermined voltage ratio; and a differential amplifier being supplied with the reference voltage and the divided voltage, and controlling the output circuit by supplying the output circuit with a voltage obtained by performing differential amplification on the reference voltage and the divided voltage according to the power supply voltage, thereby maintaining the output voltage from the output circuit at a predetermined voltage. In this circuit, since the reference voltage generator and the differential amplifier are operated with the power supply voltage, it is not necessary to supply the boosted voltage to them, whereby the output current from the booster is reduced. Therefore, undesired reduction in the boosted voltage due to an increase in the output current is suppressed. As the result, the capacitance used in the booster is reduced, and the area of the semiconductor integrated circuit is reduced.

There is provided a nonvolatile semiconductor memory which is capable of operating stably and performing high-speed access operation. A timing generation means,for generating timing signals which make a memory core unit,perform access operation uses first and second clocks of the same cycle and different phases. The timing generation means,generates timing signals for at least one first-half event among a plurality of read access events, according to the first clock, the phase of which precedes a phases of the second clock, and generates timing signals used for processing the remaining events, according to the second clock.

Nonvolatile semiconductor memory

A semiconductor memory device having nonvolatile memory cells arranged in matrix comprises and bit lines connected to drains of the memory cells. Latches provided for the respective bit lines or in the ratio of one latch to a number of bit lines, as are; transfer gates for electrically separating the respective latches from the bit lines. The device also having bit line voltage detection circuits for detecting voltages of the respective bit lines and latch reset circuits for inverting data stored in the respective latches in accordance with the outputs from the bit line voltage detection circuits. Therefore, data stored in each latch can be rewritten even by a very small memory cell current, resulting in stable program verify.

Growing community of inventors

Fukuoka, Japan

Tomoo Kimura