Kabushiki Kaisha Toshiba

Toshiba Memory Corporation

Kioxia Corporation

Tomoo Hishida

Yoshihisa Iwata

Ryota Katsumata

Masao Iwase

Sadatoshi Murakami

Masaru Kito

Yoshiaki Fukuzumi

Hideaki Aochi

Hiroyasu Tanaka

Takashi Maeda

Masaru Kidoh

Kiyotaro Itagaki

Akihiro Nitayama

Masanobu Shirakawa

Megumi Ishiduki

Yosuke Komori

Ryouhei Kirisawa

Tomoko Fujiwara

Yoshimasa Mikajiri

Junya Matsunami

Shigeto Oota

Hitoshi Iwai

A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.

Semiconductor memory having memory cell regions and other regions alternately along a bit line direction

A semiconductor memory device comprises: a semiconductor substrate; a plurality of memory units provided on the semiconductor substrate and each including a plurality of memory cells that are stacked; and a plurality of bit lines formed above each of a plurality of the memory units aligned in a column direction, an alignment pitch in a row direction of the plurality of bit lines being less than an alignment pitch in the row direction of the memory units, and an end of each of the memory units aligned in the column direction being connected to one of the plurality of bit lines formed above the plurality of the memory units aligned in the column direction.

Semiconductor memory device with a three-dimensional stacked memory cell structure

Semiconductor memory having memory cell regions and other regions alternately arranged along a bit line direction

Semiconductor memory having first and second memory cell regions separated by a third region along a bit line direction

Semiconductor memory

A non-volatile semiconductor storage device includes an memory cell array including first and second blocks, each of which includes a plurality of memory strings each having n (n: natural number) memory cells, and a optionally a peripheral circuit for controlling the memory cell array. In this non-volatile semiconductor storage device, n signal lines are arranged in the first block, and m (n&#x3e;m, m: natural number) signal lines are arranged in the second block, such that the second block size is smaller than the first block size.

Non-volatile semiconductor storage device, and memory system

A non-volatile semiconductor memory device includes first through third memory strings, a first word line group shared by first and second memory strings and a second word line group shared by second and third memory strings, the first and second word line groups extending in a first direction and disposed adjacent to each other in a second direction that is perpendicular to the first direction. The first word line group includes laminated first word lines with each upper first word line extending in the first direction less than the first word line directly below, and the second word line group includes laminated second word lines with each upper second word line extending in the first direction less than the second word line directly below.

Non-volatile semiconductor memory device

Growing community of inventors

Yokohama, Japan

Tomoo Hishida