Hitachi, Ltd.

Elpida Memory, Inc.

Renesas Technology Corp.

Other

Hitachi Ulsi Systems Co., Ltd.

Ps4 Luxco S.a.r.l.

Renesas Electronics Corporation

Hitachi, Ltd., Intellectual Property Group

Tomonori Sekiguchi

Riichiro Takemura

Kazuhiko Kajigaya

Takeshi Sakata

Katsutaka Kimura

Satoru Akiyama

Kiyoo Itoh

Tsugio Takahashi

Hideyuki Matsuoka

Toshiaki Yamanaka

Takayuki Kawahara

Satoru Hanzawa

Shinichi Miyatake

Akira Kotabe

Hiroaki Nakaya

Shinichiro Kimura

Hiromasa Noda

Kazuo Ono

Yoshitaka Nakamura

Kazushige Ayukawa

Makoto Saen

Yoshimitsu Yanagawa

Hiroki Fujisawa

Noriyuki Sakuma

Norikatsu Takaura

Akira Ide

Yasuhiro Takai

Atsushi Isobe

Shinichi Takayama

Motoyasu Terao

Takao Watanabe

Toshihiko Tanaka

Satoru Yamada

Masanao Yamaoka

Hitoshi Kume

Isamu Asano

Kousuke Okuyama

Masahiro Moniwa

Akio Nishida

Takamasa Suzuki

Ryo Nagai

Masanori Isoda

Kota Funayama

Soichiro Yoshida

Yasutoshi Yamada

Yuudai Kamada

Chisaki Takubo

Kenichi Osada

Masakazu Aoki

Kazuyuki Miyazawa

Hitoshi Tanaka

Masayuki M Nakamura

Masaharu Kinoshita

Yuko Watanabe

Shin'ichiro Kimura

Akira Maeki

Takeshi Maeda

Keiji Watanabe

Akemi Hirotsune

Mitsuaki Katagiri

Hideki Osaka

Osamu Nagashima

Yutaka Shinagawa

Nobuyuki Sugii

Toshimichi Shintani

Shuntaro Machida

Ichiro Anjo

Shiro Mazawa

Tatsuyuki Saito

Tatemi Ido

Takao Sakurai

Masayuki Nakamura

Hiroaki Furuichi

Hideo Kasai

Tatsuya Tomaru

Takashi Yunogami

Tetsufumi Kawamura

Shinya Kajiyama

Yuzuru Ohji

Makoto Mizuno

Chihiro Yoshimura

Masayoshi Hirasawa

Takenori Sato

Hiroyuki Oota

Tsuyoshi Kachi

Motokazu Ozawa

Shin&prime;ichiro Kimura

Shin' Ichiro Kimura

Ankit Sharma

An internal structure detection system includes: two kinds of sensors with different operating principles for receiving reflected waves of vibration applied to an inspection target in an investigation area; and a processing apparatus that detects an internal structure of the inspection target by using the sensor data received by the two kinds of sensors. The two kinds of sensors are deployed in the investigation area with different densities, in a distributed manner.

Internal structure detection system

A sensor terminal includes: a vibration sensor; an L-shaped attachment main body portion on which the vibration sensor is mounted and that is detachably attached to a truncated quadrangular pyramid structure portion of a valve cap attached to an opening/closing shaft portion of a water regulating valve provided in a water service pipe; side surface magnets that are provided in the attachment main body portion; and an upper surface magnet that is attached to a lower surface of a base on which the vibration sensor is mounted. Further, the truncated quadrangular pyramid structure portion includes a quadrangular upper surface and four side surfaces, and the attachment main body portion of the sensor terminal is fixed using magnet to each of the upper surface of the truncated quadrangular pyramid structure portion and at least one side surface among the four side surfaces.

Fixing structure for electronic device and water leakage detector

Provided is an acceleration sensor having a large mass in a movable portion, and realizing high impact resistance. An acceleration sensor elementincludes an upper substrate, a lower substratespaced apart from the upper substrate, and an intermediate substrateprovided between the upper substrateand the lower substrate. Each of a first movable portion, a second movable portion, a frame portion, a fixed portion, and a spring portionconstituting the intermediate substrateis configured with two layers of an upper layer and a lower layer, and a stopper portionis provided at one end of the frame portion. A distancebetween an end portion of the first movable portionor the second movable portionand an end portion of the stopper portionin the upper layer and a distancebetween an end portion of the first movable portionor the second movable portionand an end portion of the stopper portionin the lower layer are different from each other.

Acceleration sensor

An exploration system includes an artificial seismic source, sensor terminals, an environmental sensor, and a computer, wherein each of a plurality of sensor terminals is provided with a velocity or acceleration sensor which detects vibration generated by the artificial seismic source, and an identifier which is unique to the velocity or acceleration sensor; the environmental sensor detects an external environment which influences the velocity or acceleration sensor; and the computer stores a deterioration model which possibly indicates, as a degree of deterioration, performance deterioration of the velocity or acceleration sensor by providing information about the external environment as a variable, associates, with the identifier, the information about the external environment detected by the environmental sensor, stores the information about the external environment as a usage history, and determines a deterioration state of the velocity or acceleration sensor or the sensor terminal on the basis of the deterioration model.

Exploration system and diagnosing method thereof

In an acceleration sensor detecting a vibration acceleration by using torsion of a beam joining a fixed portion and a membrane, a spring constant of the beam is decreased while an increase in a chip size due to extension of the beam is prevented, so that an acceleration sensor that is highly sensitive and small in a size is provided with a low price. A sensor of a capacitance detecting type includes a membrane having a stacking structure formed of two or more layers and a plurality of beams capable of twisting so that the membrane is movable in a detecting direction, a first beam of the plurality of beams is formed of the same layer as either an upper or a lower layer of the membrane, and a second beam thereof is formed of the same layer as either an upper or a lower layer of the movable portion.

An acceleration sensor with an improved membrane (mass body) is provided. The membrane includes a moving portion, a moving portion electrically separated from the moving portion, and a mechanical junction portion that mechanically connects the moving portion and the moving portion in a y-axis direction. The mechanical junction portion includes a first portion extending in a direction having a first angle with respect to the y-axis direction and a second portion extending in a direction having a second angle different from the first angle with respect to the y-axis direction in an xy plane, and is formed to have a non-linear shape in an x-axis direction. The acceleration sensor with improved the membrane stably operates by reducing a variation in a capacity value of a detection electrode and has an excellent noise characteristic.

Acceleration sensor including improved mass body

A manufacturing device inputs design information including three-dimensional structure data, generates a manufacturing process flow, and displays the manufacturing process flow on a screen for a user to check, modify, and confirm the flow based on design information and setting information. A process method includes a first process method of a direct modeling method having an FIB method and a second process method of a semiconductor manufacturing process method which is a non-FIB method. The manufacturing device generates a plurality of manufacturing process flows by a combination of cases where each of the process methods is applied to each of the regions of the three-dimensional data. The manufacturing process flow includes a process device, the process method, a control parameter value, a process time, and a total process time for each of process steps. An output unit outputs a manufacturing process flow having, for example, the shortest total process time.

Manufacturing device, system and method for outputting a manufacturing process flow having the shortest total process time among a plurality of manufacturing process flows

A manufacturing method of a MEMS sensor includes a step of, by irradiating a first hole formed in a second layer on a semiconductor substrate with a focused ion beam for a first predetermined time, forming a first sealing film, which seals the first hole, on the first hole, and a step of, by irradiating a second hole formed in the second layer with a focused ion beam for a second predetermined time, forming a second sealing film, which seals the second hole, on the second hole. At this time, each of the first predetermined time and the second predetermined time is a time in which thermal equilibrium of the second layer is maintainable, and the step of forming the first sealing film and the step of forming the second sealing film are performed repeatedly.

Manufacturing method of MEMS sensor

It is an object of the present invention to provide a device which can be easily manufactured and obtain a ground state of an arbitrary Ising model. A semiconductor device includes a first memory cell and a second memory cell that interacts with the first memory cell, in which storage content of the first memory cell and the second memory cell is stochastically inverted. The storage content is stochastically inverted by dropping threshold voltages of the first memory cell and the second memory cell. The threshold voltages of the first and second memory cells are dropping by controlling substrate biases, power voltages, or trip points of the first and second memory cells.

Semiconductor device capable of attaining ground state in an ising model

A method for carrying out read and write operations in a synchronous memory device having a shared I/O, includes receiving a read command directed to a first internal memory bank during a first timeslot, activating the first internal memory bank to access read data at a read address requested by the read command, receiving a write command directed to a second internal memory bank during a second timeslot later than the first timeslot, determining whether a data collision between the read data for output to the shared I/O with normal read latency and write data to be received on the shared I/O with normal write latency would occur, and receiving the write data on the shared I/O with the normal write latency during a third timeslot later than the second timeslot.

Device including a plurality of memory banks and a pipeline control circuit configured to execute a command on the plurality of memory banks

A semiconductor device includes a sense amplifier circuit. The sense amplifier circuit includes a cross-coupled first transistor and second transistor that perform amplification. The sources of the cross-coupled transistors are respectively connected in series with a third transistor and a fourth transistor, and electrical current supply capability of the third and fourth transistors is controlled by a control voltage given to control electrodes of the third and fourth transistors. In a data retaining period, a minimum sub-threshold current necessary for retaining the data is flowed to the third and fourth transistors according to the control voltage, and bit line potential is maintained.

Semiconductor device

A semiconductor device is disclosed in which a plurality of memory cores are provided on a semiconductor chip. Each of the memory cores comprises: first and second circuit regions and a first and second through electrode groups. a first power supply is supplied in the first circuit region in which a data bus for parallel data is driven, and a second power supply separated from the first power supply is supplied in the second circuit region in which the parallel data and serial data are bidirectionally converted. The first through electrode group includes through electrodes supplying the first power supply to the first circuit region, and the second through electrode group includes through electrodes supplying the second power supply to the second circuit region.

Semiconductor device and memory system

A semiconductor memory device includes: a sense amplifier; a plurality of memory cell arrays; a shared MOS transistor that connects/disconnects the sense amplifier and a bit line included in the memory cell arrays; and a control circuit that controls operation of the shared MOS transistor. A part or whole of an in-sense-amplifier bit line that is a bit line connecting the sense amplifier and the shared MOS transistor is embedded in a semiconductor substrate.

Semiconductor memory device

Disclosed herein is a device that includes a delay line that includes n delay circuits cascade-connected and delays an input clock signal by k cycles, and a routing circuit that generates multi-phase clock signals having different phases based on at least a part of n output clock signals output from the n delay circuits, respectively. The n and the k are both integers more than 1 and a greatest common divisor thereof is 1.

Semiconductor device using multi-phase clock signal and information processing system including the same

A semiconductor device includes a delay buffer, and a pipeline control circuit. The pipeline control circuit controls the delay buffer to hold read data from outputting to a read/write bus for each of banks based on a read command to the each bank while the pipeline control circuit controlling the delay buffer to output write data to the read/write bus, when a next command to the each bank is a write command for the write data. The read/write bus is common to the banks.

Growing community of inventors

Tama, Japan

Tomonori Sekiguchi