Fujitsu Corporation

Tomonori Ishikawa

Teruo Yokoyama

Takeshi Igarashi

Shigehiko Sasa

Masahisa Suzuki

Shingo Kato

Shigeru Okamura

Satoshi Hiyamizu

Hidenori Ishikawa

An information processing system includes circuitry configured to identify a plurality of systems that each access at least one of a plurality of virtual machines executed by a server, generate, for each system, a value indicating whether performance of the system satisfies an agreement for the system if a virtual machine accessed by the system is stopped, determine a virtual machine to be stopped among the plurality of virtual machines based on the values.

Management system, recording medium and method for managing virtual machines

A semiconductor integrated circuit including therein a plurality of active devices comprises a semiconductor substrate, a first buffer layer on the substrate, a second buffer layer provided on the substrate and incorporating therein defects with a concentration level substantially larger than the concentration level of the defects in the first buffer layer; a device layer provided on the second buffer layer and being provided with the active devices, and a plurality of unconductive, device isolation regions formed between the active devices such that the device isolation region extends from an upper surface of the device layer toward the substrate at least beyond a lower surface of the device layer.

Semiconductor integrated circuit having a reduced side gate effect

A semiconductor device having a heterojunction and utilizing a two-dimensional electron gas formed at said the heterojunction comprises a substrate of a semi-insulating material, a first semiconductor layer of undoped indium gallium arsenide formed on the substrate, a second semiconductor layer of n-type indium aluminium arsenide formed on the first semiconductor layer and defining the heterojunction between the first semiconductor layer and the second semiconductor layer, the second semiconductor layer including an exposed region defining an exposed top surface, a third semiconductor layer of n-type gallium arsenide antimonide formed on the second semiconductor layer and having a window defined therein so as to expose the top surface of the exposed top surface region, a gate electrode formed in self-alignment with the window and in contact with the exposed top surface region of the second semiconductor layer, and ohmic electrodes formed on the cap layer in ohmic contact therewith.

Method of fabricating HEMT device with selective etching of gallium

Semiconductor device

A field effect semiconductor device which utilizes a 2DEG and is composed of a semi-insulating GaAs substrate; an i-type GaAs active layer; a superlattice structure layer which comprises a first i-type AlAs thin layer, a GaAs thin layer doped with an Si atomic plane, and a second i-type AlAs thin layer, these thin layers forming a GaAs quantum well; and n-type AlGaAs layer; and electrodes for source, drain, and gate.

High electron mobility device with intrinsic AlAs/GaAs superlattice

High electron mobility heterojunction semiconductor devices provided with a means to cause exposure of the electron source layer thereof to an electromagnetic wave allows modulation, adjustment and the like of the characteristics thereof even after completion of the production thereof, thus realizing a considerable magnitude of flexibility in the characteristics as well as considerably different modes in various embodiments, including field effect transistors which allow modulation of threshold voltage etc., connection channels or capacitors having a smaller resistance, programmable memory devices, image sensors. In addition, the high electron mobility heterojunction semiconductor devices can have a much higher operation speed than those available in the prior art.

Growing community of inventors

Fujisawa, Japan

Tomonori Ishikawa