Matsushita Electric Industrial Co., Ltd.

Tomonori Fujimoto

Kiyoto Ohta

Kiyoto Oota

Yuji Yamasaki

Masataka Kondo

Hirohito Kikukawa

Shoji Sakamoto

Yoshihiko Sumimoto

Hidefumi Otsuka

Hidefumi Ohtsuka

Kenichi Origasa

Toshitaka Uchikoba

In order to decrease the circuit scale of a power supply circuit and the area occupied by the power supply circuit over a semiconductor substrate, the power supply circuit, which supplies a supply voltage to respective parts of a memory circuit, includes a word driver power supply (first power supply circuit), a sense amplifier power supply (second power supply circuit), a bit line precharge power supply, a cell plate power supply, a substrate bias power supply, and a word line bias power supply. The word driver power supply supplies a word driver with a voltage generated by directly increasing an external supply voltage, whereas the other power supplies (e.g., the sense amplifier power supply) supply a sense amplifier, etc., with a voltage generated by decreasing the external supply voltage.

Semiconductor memory device

In a semiconductor device that needs a refresh operation for storing data, data of memory cells selected in response to a row address is read to main amplifiers through bit line pairs, sense amplifiers and data line pairs in a page-mode read operation. Thereafter, while outputting the data held in the main amplifiers to the outside, connecting transistors are turned off so as to disconnect the main amplifiers from the memory cells, and thus, the memory cells can be precharged. Also, in a page-mode write operation, while writing externally supplied input data in the main amplifiers, the memory cells can be precharged.

Semiconductor device having read and write operations corresponding to read and write row control signals

A semiconductor apparatus according to the present invention comprises a current source increasing a current volume in compliance with a rise of a temperature and an oscillation circuit driven by the current of the current source and outputting a clock for refresh control. The semiconductor apparatus, preferably, further comprises a memory device performing the refresh in synchronization with the output clock of the oscillation circuit or the divided clock thereof. The semiconductor apparatus, preferably, further comprises a constant voltage source generating a constant voltage using the current source, an oscillation circuit using the current of the current source, and a memory using the constant voltage generated by the constant voltage source as a reference voltage for a power supply circuit and performing the refresh in synchronization with the output clock of the oscillation circuit or the divided clock thereof.

Semiconductor apparatus capable of performing refresh control

A row control circuit of a semiconductor memory device includes an oscillator as a clock oscillator for generating an internal clock, a D flipflop as a refresh request signal RFRQ generation circuit for generating a refresh request signal RFRQ synchronously with the internal clock, and a delay circuit, a NAND gate, an AND gate, a D flipflop, a delay circuit, an AND gate and an OR gate as refresh circuits. By using a refresh request signal RFRQ and an active signal ACT, internal refresh is performed internally in a DRAM separately from an external refresh command.

Semiconductor memory device and semiconductor integrated circuit device

A semiconductor integrated circuit is provided in which a negative voltage generation circuit capable of supplying a memory cell transistor substrate with a stable negative voltage, independently of the fluctuation of a power source voltage or environmental conditions and the process conditions etc., is realized easily, and in which the data holding time of a memory can be secured sufficiently, and the power consumption is reduced. A voltage detection part-B included in the negative voltage generation circuit is provided with a constant voltage generation circuit-B, a measuring voltage generation circuit-B, which receives a constant voltage STDVOUT sent from the constant voltage generation circuit via a voltage supplying circuit-Band a negative voltage VBB sent from a negative voltage generation part and converts it into a measuring voltage REFVby resistors R', R&#x2032;, a first comparator AMPwhich compares the measuring voltage sent from the measuring voltage generation circuit with ground voltage and outputs the result of comparison, and an output buffer circuit-B&#x2032;, which amplifies the compared output from the first comparator and outputs it to the negative voltage generation part.

Semiconductor integrated circuit with negative voltage generation circuit, test method for the same, and recording device and communication equipment having the same

In a conventional DRAM, row addresses and column addresses are latched by DFF and decoding of addresses is started a certain time after a clock rise, and it takes a long time after the clock rise until the decoding is completed, having a problem that it is not possible to perform read/write at high speed. The present invention adopts a configuration connecting latch circuits such as the row address latch circuits and column address latch circuits using a scan chain. This makes decoding of row addresses and column addresses start when the clock is &ldquo;L&rdquo;, making it possible to complete decoding on the rise of each operation clock cycle, shorten the operation clock cycle and speed up read/write. The conventional art conducts a test on the connection between the row addresses and column addresses of the logic section and memory through an actual operation test of the entire LSI, resulting in a low circuit failure detection rate. The present invention conducts this test through a scan test, making it possible to automatically create test patterns with high circuit failure detection rate.

Semiconductor device having integrated memory and logic

A semiconductor integrated circuit includes a plurality of semiconductor memory devices implemented as DRAMs and an output selector on the same chip. External terminals of the chip include: terminals for inputting an inverted row address strobe signal /RAS to the respective semiconductor memory devices individually; and common terminals for inputting PRAUT, SLF, /CAS, ADR, /WE, /OE, CLK and TMODE signals to all the memory devices. The output signals TDQ, SRAS, MOUT and BITST of the semiconductor memory devices are controlled by the output selector, passed through a common test bus and then output from a common external terminal.

Semiconductor device

A boosting circuit included in a semiconductor integrated circuit for efficiently stabilizing a boosted potential, including a plurality of boosting circuits and a timing control circuit for distributing the operations of the boosting circuits. Boosting operations per operating cycle of a memory increase in number so as to suppress a reduction in boosted source potential, the reduction being caused by consumption. Moreover, it is possible to perform a boosting operation in a time period equal to that of consuming boosted source potential, resulting in an efficient boosting operation.

Semiconductor circuit having a detection circuit for controlling a power boosting circuit

A semiconductor device capable of refreshing a plurality of memory cells. In operation, when requesting a data read operation a /row selection control signal is input to a set/reset circuit of a row selection control circuit, whereby an H-level hidden refresh control signal is output and an internal row selection control signal transitions to the H level. As a result, an intended word line is selected, and a refresh operation is initiated. Then, a sense amplifier activation completion signal SEND is input via a delay circuit to the set/reset circuit after completion of a sense operation, and the internal row selection control signal transitions to the L level. The sense amplifier activation completion signal SEND is input to another set/reset circuit after passing through three delay circuits, and an RW row selection control signal transitions to the H level, thereby performing a data read operation.

A semiconductor memory device including a memory cell array having a plurality of memory cells requiring refresh, a first internal address generation circuit, a timer circuit that operates in response to a control signal input externally and generates a periodic pulse signal, and a second internal address generation circuit that operates in response to an output signal from the timer circuit. The first internal address generation circuit generates a refresh address of the entire memory region, and the second internal address generation circuit generates a refresh address of a certain part of the regions. By carrying out refresh of only a part of the memory required to be retained, the electric power consumption can be reduced.

Semiconductor integrated circuit

To realize a semiconductor memory which can be operated at a low frequency without reducing a data transfer rate, the semiconductor memory according to the invention is configured so that a series of operation can be finished in two clock cycles of row address strobe operation and column address strobe operation for operating DRAM. Timing for turning a sense amplifier activation signal SE at a high level after delay time determined by a first delay element since a leading edge of a clock pulse CLK that turns a row address strobe pulse (/RAS) at a low level and activating a sense amplifier sequence is generated. Also, timing for starting read operation and write operation since a leading edge of the clock pulse CLK at which a column address strobe pulse (/CAS) is turned at a low level, turning the sense amplifier activation signal SE at a low level, turning a bit line precharge signal EQPR at a high level and starting precharge operation when the termination of reading and writing is detected is acquired.

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Osaka, Japan

Tomonori Fujimoto