Seiko Instruments Inc

Ablic Inc.

Sii Semiconductor Corporation

Sti Semiconductor Corporation

Tomomitsu Risaki

Shoji Nakanishi

Koichi Shimazaki

Jun Osanai

Yuichiro Kitajima

Takeshi Koyama

Hitomi Sakurai

In order to inhibit forming cracks under a pad opening during ball bonding without increasing a chip size, a protective film includes a pad opening that exposes a part of a topmost layer metal film of the chip. A second metal film provided under the pad opening has a ring shape that defines a rectangular opening under the pad opening. The opening edge of the opening in the second metal film extends inwardly beyond the edge of the overlying pad opening. Vias connect the second metal film and the topmost layer metal film, and all of these vias are located outside the pad opening in plan view.

Semiconductor device and ball bonder

Provided is a semiconductor device which has a non-volatile memory including: a semiconductor substrate; a tunnel insulating film formed on a surface of the semiconductor device; a floating gate formed on the tunnel insulating film; a memory cell transistor drain region and a memory cell transistor source region formed from the surface to an inside of the semiconductor substrate in a vicinity of both ends of the floating gate; a first interface formed between the semiconductor substrate and the tunnel insulating film; and a second interface formed between the floating gate and the tunnel insulating film. The first interface and the second interface form an uneven structure having a curvature that changes at an identical period with respect to a place in sectional view.

Semiconductor device and method of manufacturing the same

When an ESD element is operated, for the purpose of suppressing heat generation and causing uniform current to flow through all channels of all transistors included in the ESD element, various substrate potentials existing in the transistors and the channels of a multi finger type ESD element are electrically connected via a low resistance substrate, and further, are set to a potential that is different from a Vss potential. In this manner, the current is uniformized and heat generation is suppressed through low voltage operation to improve an ESD tolerance.

Semiconductor device having ESD element

Provided is a semiconductor device, which prevents unnecessary voltage drop in a MOS transistor that is connected in series in a location between a booster circuit and a memory main body portion, to thereby operate on a low voltage and improve the ON/OFF ratio so that chip size shrinking and memory performance improvement are accomplished simultaneously. In a semiconductor memory device including a memory transistor portion and a select transistor portion, at least the select transistor portion is formed of a fin-shaped single-crystal semiconductor thin film.

Semiconductor memory device and method of manufacturing the same

A semiconductor memory device includes a first floating gate and a second floating gate of conductivity types with different polarities. Injection of electrons into the first floating gate via a tunnel insulating film is stored through a decrease in holes in a valence band of the second floating gate, and ejection of electrons from the first floating gate via the tunnel insulating film is stored through an increase in holes in the valence band of the second floating gate.

Semiconductor memory device having first and second floating gates of different polarity

In order to provide a semiconductor device having a high ESD tolerance, a source wiring () is formed on a gate () and a source () in a region of an NMOS transistor (). The source wiring () electrically connects the gate (), the source (), and a ground terminal. A drain wiring () is formed on a drain () in the region of the NMOS transistor () . The drain wiring () electrically connects the drain () and a pad () serving as an external connection electrode. Moreover, in the region of the NMOS transistor (), the drain wiring () has the same wiring width as the source wiring ().

Semiconductor device

A semiconductor device has a semiconductor substrate provided with a scribe region and an IC region. A first insulating film is disposed on the semiconductor substrate across the scribe region and the IC region. At least one separation groove is provided in the first insulating film in the scribe region. Side walls made of a plug metal film are formed only on respective lateral walls of the separation groove so that the plug metal film on the lateral walls does not extend out of the separation groove and does not exist on an upper surface of the first insulating film. A second insulating film covers at least the side walls formed on the respective lateral walls of the separation groove so that the side walls are disposed under the second insulating film.

Semiconductor device and manufacturing method therefor

A semiconductor device has a semiconductor substrate and a breakdown voltage adjusting first conductivity type low concentration region provided on the semiconductor substrate. A second conductivity type high concentration region is provided near a surface within the breakdown voltage adjusting first conductivity type low concentration region so as to be surrounded by the first conductivity type low concentration region but not surrounded by any low concentration region other than the first conductivity type low concentration region. A first conductivity type high concentration region is provided on the surface within the breakdown voltage adjusting first conductivity type low concentration region without being held in contact with the second conductivity type high concentration region.

Provided is a semiconductor device which uses a comb-like N-type MOS transistor as an ESD protection element and is capable of uniformly operating the entire comb-like N-type MOS transistor. By adjusting a length L of a gate electrode of the N-type MOS transistor used as the ESD protection element in accordance with the distance from a contact for fixing a substrate potential, which is provided on a guard ring around an outer periphery, respective portion of N-type MOS transistor represented as a comb teeth uniformly enter snap-back operation, permitting avoidance of local concentration of current and obtainment of a desired ESD tolerance.

Trench portions () are formed in a well () in order to provide unevenness in the well (). A gate electrode () is formed via an insulating film () on the upper surface and inside of the trench portions (). A source region () is formed on one side of the gate electrode () in a gate length direction while a drain region () on another side. Both of the source region () and the drain region () are formed down to near the bottom portion of the gate electrode (). By deeply forming the source region () and the drain region (), current uniformly flows through the whole trench portions (), and the unevenness formed in the well () increases the effective gate width to decrease the on-resistance of a semiconductor deviceand to enhance the drivability thereof.

Trench MOS transistor and method of manufacturing the same

Provided is a semiconductor device comprising: a PW layer formed at a surface of a semiconductor substrate; an NW layer formed at the surface of the semiconductor substrate to be in contact with the PW layer; a p+ base layer formed at the surface of the semiconductor substrate in the PW layer; an n+ collector layer formed at the surface of the semiconductor substrate in the NW layer; an n+ emitter layer located between the p+ base layer and the n+ collector layer and formed at the surface of the semiconductor substrate in the PW layer; and an n&#xb1; layer formed between the n+ collector layer and the PW layer to be in contact with the n+ collector layer.

A semiconductor device has a well region formed of a first conductivity type semiconductor at a predetermined depth from a surface of a substrate, trenches formed in the well region, and a gate insulating film formed on surfaces of concave and convex portions of the trenches. A first gate electrode is embedded inside the trenches, and a second gate electrode is formed on the substrate in contact with the first gate electrode in regions of the concave and convex portions excluding vicinities of both ends of the trenches. Source and drain regions of a second conductivity type are formed from a part of a surface of the semiconductor so as to extend deeper in a side surface of the concave portion of each trench than in the surface of the convex portion of each trench and shallower than the depth of the well region.

Semiconductor device having a trench structure and method for manufacturing the same

In a well region, an irregular structure is formed in a gate width direction, and a gate electrode is formed in concave portions and on top surfaces of convex portions via an insulating film. Upper and lower source regions are formed on one side of the gate electrode in a gate length direction, and upper and lower drain regions are formed on the other side thereof. By thus forming the lower source and drain regions in the source and drain regions, current concentration occurring in an upper portion of a channel region, which is generated as the gate length becomes shorter, may be suppressed and a current may be allowed to flow uniformly in the entire channel region, and hence an effective gate width is made wider owing to the irregular structure formed in the well region. Accordingly, an on-resistance of a semiconductor device is reduced to enhance driving performance.

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Chiba, Japan

Tomomitsu Risaki