Sanyo Electric Co., Ltd.

Panasonic Intellectual Property Management Co., Ltd.

Tomomichi Nakai

Toshio Nakakuki

Takeshi Nakashima

Kazuo Ishimoto

Yoshihito Higashitsutsumi

Takashi Tanimoto

Tatsuya Takahashi

Takehito Ike

Yoshimitsu Noguchi

Takayoshi Abe

Hiroshi Saeki

Masato Teratani

In the present invention, a main switch circuit () is provided between an electric power line (PL), to which voltage outputted from a solar cell () is applied, and a battery module (). A protection circuit () turns OFF the main switch circuit () to protect the battery module () from overcharging when the voltage (VBAT) of the battery module () is equal to or greater than an upper limit voltage. The voltage outputted from the solar cell () is set so as to be greater than the upper limit voltage to allow the battery module () to be charged to the upper limit voltage. When a charge ON command signal has been received, a control unit () turns ON only a sub-switch circuit () to introduce current from the solar cell () into a parallel circuit () and to suppress the voltage (VPL) of the power line (PL) to less than the upper limit voltage before turning ON the main switch circuit ().

Switching device

A ground fault detection circuit includes: a first switch circuit that connects/disconnects a first path between a positive bus bar and a ground potential section, the positive bus bar being connected to positive electrodes of secondary battery units through a field-effect transistor including a parasitic diode; a second switch circuit that connects/disconnects a second path between a negative bus bar and a ground potential section, the negative bus bar being connected to negative electrodes of the secondary battery units; and a ground fault detection unit that detects a ground fault of the positive bus bar or the negative bus bar based on an electric current flowing through the first path or the second path.

Ground fault detection circuit and ground fault detection apparatus

An image signal is input to two LPFs having different transmission characteristics. A selector chooses one of outputs of the respective LPFs and delivers the chosen output to a gamma correction circuit. The switching of the selector is controlled by a filter control circuit. In the filter control circuit, a comparator compares an exposure time E of a current frame with a threshold value R. The selector is controlled so as to select an output of one of the LPFs that has a lower cutoff frequency and a greater noise component elimination effect than the other LPF does if the exposure time E is longer than or equal to the threshold value R.

Image signal processing apparatus for setting a noise component attenuation characteristic

In exposure control of an imaging apparatus, if a vertical scanning period is enlarged to increase an exposure time when the exposure time reaches an upper limit value, there occurs a problem in that a frame rate is reduced. Accordingly, when a subject is dark, an auto exposure control circuit sets the vertical scanning period V to a standard value Vst, increases the exposure time E to the upper limit value Emax (P) and then increases a gain &#x3b1; of an AGC circuit (P). If the image is still dark even when the gain &#x3b1; reaches the upper limit value &#x3b1; max, the auto exposure control circuit switches the vertical scanning period V to an enlarged value Vex and thus more increases the exposure time E (P).

Imaging apparatus and control circuit of imaging device

Image data of a target pixel and peripheral pixels are stored in a memory. Using a most significant bit extractor circuit, 4 most significant bits of data are extracted from each image data. A histogram circuit generates a histogram of the extracted 4-bit data. Referring to the histogram, a data processor circuit () replaces the image data of the target pixel with a maximum value of the numbers of pixels having the same level and outputs the processed data. Then, a digit-complementing circuit converts the data output from the data processor circuit to 8-bit data and outputs the converted data. In this manner, a regular image is converted into an image similar to a draft-design image.

Image data processor and image data processing method

An imaging apparatus having a solid-state image sensor, such as a CCD, accumulates information charges corresponding to an image of an object and generates an image signal using the stored charges. A driver provides clock signals to the sensor which define vertical and horizontal scan periods, so that the information charges are accumulated in a predetermined exposure period, in accordance with a timing signal. A first exposure information generating circuit determines whether a level of the image signal is within an appropriate range and produces first exposure information based on the determination results. A second exposure information generating circuit calculates second exposure information using the image signal. A selector selects the first exposure information when the level of the image signal is outside of the predetermined exposure period and selects the second exposure information when the image signal is within the predetermined exposure period. A timing control circuit receives the selected exposure information from the selector and generates the timing signal.

Method and apparatus for controlling an exposure period of a solid-state imaging apparatus based upon an image signal output

A frame transfer type solid-state imaging apparatus has a matrix of pixels which store information charges corresponding to a received image. The information charges are moved from the pixels to vertical transfer registers, and then to a horizontal transfer register, prior to being stored. A timing control circuit generates a vertical scan timing signal and a horizontal scan timing signal using a divided clock signal. A horizontal drive circuit generates a horizontal transfer clock using the divided clock signal and the horizontal scan timing signal. The horizontal transfer clock is used to move the information charges from the vertical transfer registers to the horizontal transfer register. A vertical drive circuit generates a vertical transfer clock using a reference clock signal and the vertical scan timing signal. The vertical transfer clock is used to move the information charges from the pixels to the vertical transfer registers. The divided clock signal is generated by dividing the reference clock signal by a predetermined ratio, such that the divided clock signal is longer than the reference clock signal. By generating the vertical transfer clock using the reference clock, and not the longer, divided clock, the resulting image does not have an increase in smear components.

Clock signal generator for solid-state imaging apparatus

Exposure control for a solid-state imaging apparatus can be completed in a short time. First exposure information D and second exposure information D are prepared. The first exposure information D is for adjustment of an exposure time L for a CCD ( ) through extension or reduction in the unit of one horizontal scanning period; the second exposure information D is for direct designation of an exposure time L. When the power is switched on, the second exposure information D is selected for supply to a timing control circuit ( ). After a lapse of a predetermined time, the first exposure information D is then selected.

Solid-state imaging apparatus

A solid-state imaging apparatus having a CCD image capturing circuit includes an exposure time control circuit which analyzes the image signal generated by the image capturing circuit and generates a control signal to adjust an image exposure time. A balance control circuit also receives the control signal and updates gain control information used by an image processing circuit that generates color difference data (U/V data) from the image signal.

Exposure control circuit for solid-state imaging apparatus

A signal level adjusting circuit for performing adjustment of signal levels in which the levels of individual image signals are made uniform so as to provide greater use of a dynamic range on an image sensor without deterioration to resolution.

Level adjusting circuit of color image signal

A plurality of setting data stored in a serial register 11 and externally supplied replacement data are inputted into selectors 12. Either of the setting or replacement data is provided to the respective one of the setting inputs S.sub.1 -S.sub.n in a digital signal processing unit 10. Each of the selectors 12 usually selects the setting data. When a selector 12 is specified by a decoder 13 based on address data, it only selects the replacement data. When the replacement and address data are suitably set, the computation condition of the digital signal processing unit 10 can be partially changed without rewriting of the setting data in the serial register 11.

Signal processing apparatus capable of computing replacement data

An image pickup section includes the number of pixels in the vertical direction which is decreased one-half less than the number of scan lines. A signal containing image components is outputted every one horizontal line. The horizontal line containing the image components in an odd field is offset from that in an even field by one line. In both the odd and even fields, leach of these image signals are multiplexed on a signal delayed by one horizontal scan period to form an image signal which contains the same image components for each two horizontal lines. This image signal is then displayed in the non-interlace manner.

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Ogaki, Japan

Tomomichi Nakai