Fanuc Corporation

Tomomasa Nakama

Teruki Nakasato

Kei Hagihara

The present invention provides a SerDes interface circuit and a control device which make it possible to use the same SerDes to perform data transfer of different communication rates. The present invention includes: a FIFO that inputs a first clock of a first frequency, first transmission data based on the first clock, and a second clock of a second frequency which is different from the first frequency, and that outputs the first transmission data on the basis of the second clock in the order of input; a flipflop that fetches and holds the FIFO output on the basis of the second clock; and an output state machine operating with the second clock that inputs the FIFO output and the flipflop output, and generates parallel data in which the same data corresponding to the first transmission data is consecutive.

SerDes interface circuit and control device

A master communication device of this communication system comprises: a generation unit that generates transmission data consisting of consecutive data to all slave communication devices following one header; and a transmission unit that transmits the transmission data generated by the generation unit at the fastest cycle, among communication cycles requested by the plurality of slave communication devices. Each of the plurality of slave communication devices of the communication system comprises: a storage unit that adds information indicating reliability to data received from the master communication device and stores the same; a comparison unit that compares the reliability of subsequently received data and the reliability of the data stored in the storage unit; and a selection unit that selects the data stored in the storage unit if the reliability of the data stored in the storage unit is higher than the reliability of the data subsequently received by the comparison unit.

Communication system

According to a synchronization method, a basic timing signal generation circuit generates a basic timing signal. A communication control circuit generates a first communication cycle timing signal, measures an input difference between the basic timing signal and a predetermined one of first communication cycle timing signals, divides a compensation value responsive to the input difference by the number of first communication cycle timing signals, adds up a value resulting from the division in a communication cycle, compensates for timing of generating the first communication cycle timing signal with timing equal to or greater than a predetermined value, and transmits timing compensation data to external equipment. The external equipment generates a second communication cycle timing signal, compensates for timing of generating the second communication cycle timing signal based on timing of receipt of the timing compensation data, and synchronizes with the first communication cycle timing signal.

Synchronization method and controller

A numerical controller in the present invention includes a bus trace circuit configured to fetch a bus cycle satisfying preset conditions, an alarm history, an alarm data acquisition table in which whether to acquire trace data is recorded for each alarm, and a trace circuit setting table in which fetching conditions of the bus cycle of the bus trace circuit are recorded for each alarm, and identifies an alarm for which the trace data is to be fetched from the alarm history and the alarm data acquisition table, reads the fetching conditions of the bus cycle corresponding to the alarm from the trace circuit setting table, sets the fetching conditions to the bus trace circuit, and acquires the trace data of the bus cycle based on the fetching conditions that are set through the bus trace circuit.

Numerical controller and numerical control system in which the controller is connected by network

A device includes a recovery unit that separates recovery data and a recovery clock from input data, a first detection unit that detects a timing at which a phase difference between a generated processing clock and the recovery clock is zero, a second detection unit that detects a synchronization code included in the recovery data using the recovery clock, and a calculation unit that calculates a phase difference between the synchronization code and the processing clock using a ratio between a first number of clock generation times of the processing clock in a period from a first timing at which the detected phase difference is zero to a second timing at which the phase difference is subsequently zero, and a second number of clock generation times of the processing clock in a period from the first timing to a third timing in which the synchronization code is detected.

Phase difference estimation device and communication device having the phase difference estimation device

In a data recovery circuit, the position of an edge is detected from parallel data acquired by oversampling data received through serial communication, the position of a next edge is estimated, the estimated position of the edge is compared with the detected position of the actual edge, and the sampling position of the parallel data is adjusted based on a result of the comparison. As a result, an oversampling clock can be set to a maximum frequency, and accordingly, the precision of the data recovery circuit can be improved.

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Yamanashi, Japan

Tomomasa Nakama