Micron Technology Incorporated

Tomoko Ogura Iwasaki

Lawrence Celso Miranda

Sheyang Ning

Manik Advani

Jianmin Huang

Aparna U Limaye

Avani F Trivedi

Tracy D Evans

Erwin E Yu

Eric N Lee

Yoshihiko Kamata

Jeffrey S McNeil, Jr

Hong-Yan Chen

Zhengyi Zhang

Foroozan Sarah Koushan

Ji-Hye Gale Shin

Dan Xu

Jayasree Nayar

Aaron S Yip

Luyen Tien Vu

Kalyan Chakravarthy Kavalipurapu

Yunfei Xu

Kishore Kumar Muchherla

Haitao Liu

Paolo Tessariol

Ting Luo

June Lee

Richard J Hill

Carla L Christensen

Jun Xu

Kulachet Tanpairoj

Hao Nguyen

Dheeraj Srinivasan

Samir Mittal

Jiewei Chen

Naveen Kaushik

Kyle A Ritter

Mithun Kumar Ramasahayam

Yoshiaki Fukuzumi

Peter Sean Feeley

Violante Moschiano

Ramin Ghodsi

Steven Moyer

Nabeel Meeramohideen Mohamed

Shruthi Kumara Vadivel

Deepti Verma

Tyler L Betz

Surendranath C Eruvuru

Priya Vemparala Guruswamy

Sue-Fern Ng

Kari Crane

Pamela Castalino

A memory device includes a first pillar coupled with a first data line, a second pillar coupled with a second data line, and wordlines coupled with first and second pillars. Control logic may cause wordlines to be discharged after a program pulse is applied to selected wordline. The control logic may apply a supply voltage to second data line to cause a voltage of second pillar to float. The control logic may apply a ground voltage to the first data line to inhibit soft erase associated with the selected wordline via first pillar.

Fast bit erase for upper tail tightening of threshold voltage distributions

Memories might include an array of memory cells having a plurality of strings of series-connected memory cells and a controller configured to cause to memory to access a first string of series-connected memory cells of the plurality of strings of series-connected memory cells in a first mode of operation for volatile storage of data to the first string of series-connected memory cells, and access a second string of series-connected memory cells of the plurality of strings of series-connected memory cells in a second mode of operation for non-volatile storage of respective data to each memory cell of a plurality of memory cells of the second string of series-connected memory cells

Volatile data storage in NAND memory

Control logic in a memory device causes a pass voltage to be applied to a plurality of wordlines of a block of a memory array of the memory device, the block comprising a plurality of sub-blocks, and the pass voltage to boost a channel potential of each of the plurality of sub-blocks to a boost voltage. The control logic further selectively discharges the boost voltage from one or more of the plurality of sub-blocks according to a data pattern representing a sequence of bits to be programmed to respective memory cells of the plurality of sub-blocks. In addition, the control logic causes a single programming pulse to be applied to a selected wordline of the plurality of wordlines of the block to program the respective memory cells of the plurality of sub-blocks according to the data pattern.

Dynamic latches above a three-dimensional non-volatile memory array

Double single level cell program in a memory device

Control logic in a memory device initiates a program operation including application of a set of programming pulses to a wordline associated with one or more memory cells of a memory array to be programmed to a set of programming levels, where each programming level of the set of programming levels is programmed by each programming pulse. The control logic determines that a program voltage of a programming pulse of the set of programming pulses reaches a maximum program voltage level. In response to the determining, during a subsequent programming pulse following the programming pulse, adjusting a first voltage associated with boosting a pillar voltage, a second voltage applied to a bitline, and a third voltage applied to the wordline to establish a subsequent program voltage of the subsequent programming pulse that is below the maximum program voltage level.

Establishing bitline, wordline and boost voltages to manage a maximum program voltage level during all levels programming of a memory device

Control logic in a memory device identifies memory cells of a memory array configured as single-level cell (SLC) memory, where the memory cells include two or more memory cells programmed during a program phase and associated with a selected wordline of the memory array. The control logic further causes a program verify voltage to be applied to the selected wordline during a ganged SLC verify operation to be performed concurrently on the memory cells. In response to the memory cells failing to pass ganged SLC verify operation, the control logic further: copies first data, which is associated with a first memory cell, into the data recovery latch; causes a program verify operation to be performed separately on the first memory cell; and in response to the first memory cell reaching a program verify voltage, causes an inhibit of the first memory cell from further programming.

Single-level cell program-verify, latch-limited data recovery

A system for manufacturing a memory device forms a memory array comprising a plurality of memory cells arranged in a plurality of memory strings along a plurality of memory array pillars and forms a logic layer disposed above the memory array, the logic layer comprising a plurality of latches arranged along a plurality of logic layer latch pillars, the plurality of latches to store a multi-bit data pattern representing a sequence of bits to be programmed to the plurality of memory cells of the memory array.

Creating dynamic latches above a three-dimensional non-volatile memory array

Control logic in a memory device causes a programming pulse of a set of programming pulses to be applied to a wordline associated with a memory cell of a memory device, where the memory cell is to be programmed to a target voltage level representing a first programming level. At a first time, first data is caused to be stored in a cache, the first data indicating that a threshold voltage of a memory cell exceeds the target voltage level. At a second time, the cache is caused to be refreshed to store second data indicating that the threshold voltage of the memory cell is less than the target voltage level. In view of the second data, a level shifting operation associated with the memory cell is caused to be executed.

In-line programming adjustment of a memory cell in a memory sub-system

Described are systems and methods for all level coarse/fine programming of memory cells. An example memory device comprises: a memory array comprising a plurality of memory cells electrically coupled to a plurality of wordlines and a plurality of bitlines; and a controller coupled to the memory array, the controller to perform operations comprising: identifying a set of memory cells for performing a memory programming operation, wherein the memory cells are electrically coupled to a target wordline and a set of target bitlines; causing a first voltage to be applied to the target wordline, wherein the first voltage is incremented every time period over a number of time periods that corresponds to a number of threshold voltages to be programmed; causing a second voltage to be applied to a first bitline over the number of time periods; causing a third voltage to be applied to a second bitline, wherein the third voltage is incremented during a second time period of the number of time periods, wherein the second time period follows a first time period; causing a fourth voltage to be applied to a third bitline, wherein the fourth voltage is incremented during a third time period of the number of time periods, wherein the third time period follows the second time period; and causing a fifth voltage to be applied to a fourth bitline over the number of time periods.

All level coarse/fine programming of memory cells

Described are systems and methods for concurrent slow-fast memory cell programming. An example memory device comprises: a memory array comprising a plurality of memory cells electrically coupled to a plurality of wordlines and a plurality of bitlines; and a controller coupled to the memory array, the controller to perform operations comprising: identifying a set of memory cells for performing a memory programming operation, wherein the set of memory cells are electrically coupled to a target wordline and one or more target bitlines; causing a first programming pulse to be performed by applying a first programming voltage to the target wordline; classifying, by a processing device, the set of memory cells into a first subset of memory cells and a second subset of memory cells based on their respective threshold voltages; causing a first bias voltage to be applied to a first target bitline connected to the first subset of memory cells; causing a second bias voltage to be applied to a second target bitline connected to the second subset of memory cells; and causing a second programing voltage to be applied to the target wordline, wherein the second programming voltage exceeds the first programing voltage.

Concurrent slow-fast memory cell programming

Control logic in a memory device cause a programming pulse to be applied to a set of wordlines including a first set of even-numbered wordlines corresponding to a first set of memory cells to be erased and a second set of odd-numbered wordlines corresponding to a second set of memory cells to be erased, where a set of electrons are injected into a first set of gate regions, a second set of gate regions, and a set of inter-cell regions of a charge trap (CT) layer of the memory device. The control logic executes a first erase cycle on the first set of even-numbered wordlines to remove a first subset of electrons from the first set of gate regions corresponding to the first set of even-numbered wordlines. The control logic executes a second erase cycle on the second set of odd-numbered wordlines to remove a second subset of electrons from the second set of gate regions corresponding to the second set of even-numbered wordlines.

Erase operation with electron injection for reduction of cell-to-cell interference in a memory sub-system

Memory array structures might include a first conductive plate connected to memory cells of a first dummy block of memory cells and to memory cells of a second dummy block of memory cells on opposing sides of a first isolation region; a second conductive plate connected to memory cells of the first dummy block of memory cells and to memory cells of the second dummy block of memory cells on opposing sides of a second isolation region; first and second conductors selectively connected to a first global access line, and connected to the first conductive plate on opposing sides of the first isolation region; third and fourth conductors selectively connected to a second global access line, and connected to the second conductive plate on opposing sides of the second isolation region; and a fifth conductor connected to the third conductor and connected to the second conductor.

Memory array structures and methods of forming memory array structures

Methods and devices related to a cellular signal mesh network are described. In an example, a method can include determining, via a processing resource of a first computing device, whether a cellular signal of the first computing device is below a threshold cellular signal, transmitting from the first computing device to a second computing device first signaling including data representing a request for operational data of the second computing device in response to determining that the cellular signal of the first computing device is below the threshold cellular signal, receiving from the second computing device second signaling comprising the operational data of the second computing device, and transmitting from the first computing device to the second computing device third signaling including data representing at least one of: a voice call, a video call, or a message in response to receiving the second signaling comprising the operational data.

Cellular signal mesh network

A memory device includes a content addressable memory (CAM) block storing a plurality of stored search keys. The memory device further includes control logic that determines a first number of memory cells in at least one string of the CAM block storing one of the plurality of stored search keys, the first number of memory cells storing a first logical value, and stores a calculated parity value representing the first number of memory cells in a page cache associated with the CAM block. The control logic further reads stored parity data from one or more memory cells in the at least one string, the one or more memory cells connected to one or more additional wordlines in the CAM block, and compares the calculated parity value to the stored parity data to determine whether an error is present in the one of the plurality of stored search keys in the CAM block.

Health scan for content addressable memory

A memory system includes a memory device comprising a content addressable memory (CAM) block storing a plurality of stored search keys. The memory system further includes a processing device that receives an input search key and identifies, from the plurality of stored search keys in the CAM block, multiple redundant copies of a stored search key that match the input search key. The processing device further determining whether a number of the multiple redundant copies of the stored search key that match the input search key satisfies a threshold criterion. Responsive to the number of the multiple redundant copies of the stored search key that match the input search key satisfying the threshold criterion, the processing device determines a match result for the input search key.

Redundancy and majority voting in a key-value data storage system using content addressable memory

Growing community of inventors

San Jose, CA, United States of America

Tomoko Ogura Iwasaki