Nec Electronics Corporation

Renesas Electronics Corporation

Tomoko Matsuda

Hiroshi Kimura

Takashi Ide

Takamasa Itou

Hiroshi Kitajima

A semiconductor device includes a silicon substrate, and a NiSi layer provided on the silicon substrate aiming to suppress oxidation of the surface of a NiSi layer and the resistivity increase. The NiSi layer includes a bottom NiSi region and a top NiSi region. The bottom NiSi region provided in contact with silicon surface, and containing substantially no nitrogen. The top NiSi region is a nitrided NiSi region provided in contact with the bottom NiSi region, and containing nitrogen. The NiSi layer has a total thickness of 50 nm or below.

Semiconductor device

Semiconductor device and method of manufacturing the same

Method for manufacturing a semiconductor device, includes: forming a layer of dicobalt monosilicide (CoSi) or of cobalt (Co) on a device-forming surface of a silicon substrate in a sputter apparatus, by utilizing a predetermined temperature profile; elevating a temperature of the silicon substrate to a predetermined temperature T, which is equal to or higher than 600&#xb0; C., conducted after forming the layer of Co or CoSi; and forming a layer of monocobalt monosilicide (CoSi) on the device-forming surface of the silicon substrate at a temperature equal to or higher than T, conducted after heating the silicon substrate to T, wherein, the silicon substrate is elevated to a temperature between a highest reachable temperature Tof the silicon substrate during forming the layer of Co or CoSi and the temperature Tat a temperature ramp rate of equal to or higher than 50&#xb0; C./sec.

Method of manufacturing semiconductor device

A junction leak current of a transistor including a silicide layer provided on a source/drain region is to be suppressed. After forming a gate electrode over a chip-side surface of a silicon substrate, an insulating layer is formed over the gate electrode. The insulating layer is etched back so as to form a sidewall that covers the sidewall of the gate electrode, and a region adjacent to the sidewall on the chip-side surface of the silicon substrate, where a source/drain region is to be formed, is etched so as to form a generally horizontal scraped section on the chip-side surface. Then a dopant is implanted to the silicon substrate around the gate electrode, to thereby form the source/drain region. On the chip-side surface of the silicon substrate where the gate electrode is provided, a Ni layer is formed, so that the Ni layer is reacted with the silicon substrate thus to form a Ni-silicide layer.

A method of manufacturing a semiconductor device that can inhibit transformation of an NiSi layer into a disilicide is to be provided. An NiSi layer is formed on gate electrodes and source/drain regions in both of a P-MOS transistor and a N-MOS transistor (a silicide layer formation step). A direct nitride layer is formed on an entire region including the NiSi layer (a nitride layer formation step). Then an element that can increase heat-resisting temperature of the NiSi layer is implanted into the NiSi layer (an element implantation step). As a result, heat-resisting property of the NiSi layer can be increased, and thereby the NiSi layer can be inhibited from being transformed into a disilicide.

Growing community of inventors

Kanagawa, Japan

Tomoko Matsuda