Kabushiki Kaisha Toshiba

Tomoko Kitazawa

Tetsuya Iizuka

Yasuyuki Hanazawa

Yuko Kizu

Katsuhiko Inada

Yoshihiro Asai

Takuya Shimano

According to one embodiment, a system LSI verification system that verifies a processor module included in a system LSI, the system comprising: a circuit description storage that stores description data that describes a design of the processor module; a verification task generator that generates a verification task file based on the description data and a verification environment specification file in which specifications of a verification environment are described; a test program storage that stores a test program including an environment command function for starting the verification task; and a logical simulator that performs a logical simulation according to the test program.

System LSI verification system and system LSI verification method

A liquid crystal display device is composed of an array substrate which includes a matrix array of pixel electrodes, a plurality of scanning liness formed along rows of the pixel electrodes, each for selecting the pixel electrodes of a corresponding row, a plurality of signal lines formed along columns of the pixel electrodes, for setting potentials of the pixel electrodes of a selected row, and an alignment film formed to cover the pixel electrodes, the scanning lines and the signal lines, a counter substrate which includes a counter electrode facing the matrix array of pixel electrodes, and an alignment film formed to cover the counter electrode, and a liquid crystal layer which is held between the array substrate and the counter substrate and has liquid crystal molecules aligned by the alignment films of the array and counter substrates. In the liquid crystal display device, the scanning line is formed to have a cutout at an intersection of the scanning and signal lines located on a side corresponding to pretilt-base ends of the liquid crystal molecules aligned by the alignment film of the array substrate, and the cutout is determined to reduce an electric field produced in the liquid crystal layer between the scanning line and the pixel electrode.

Liquid crystal display device

An aperture rate of an active matrix substrate using TFTs can be improved, a short circuit can be prevent from being caused between a pixel electrode and a signal line, or a display defectiveness due to a coupling capacitor can be prevented, and display definition can be improved. A pixel electrode patterned by a back surface exposure technique is formed on a different surface by the presence of an insulating protection film. A source electrode and the pixel electrode are connected to each other by a first contact electrode formed of a transparent conductive film to be connected to a first contact hole formed through the insulating protection film. Since a connecting portion between the source electrode and the pixel electrode through the contact hole and a connecting portion between the pixel electrode and an auxiliary capacitor electrode are transparent conductive films, an aperture rate is not reduced. The pixel electrode and the signal line are formed on the different surface by the presence of the insulating protection film. As a result, no short circuit occurs therebetween. The defectiveness of points caused by the short circuit can be prevented from being generated.

Liquid crystal display device having a TFT switch composed of a separate

The present invention relates to the structure of an active matrix type liquid crystal display device in which a channel length of a thin film transistor without increasing resistance of a scanning line region to improve a switching characteristic. A slit is formed at the channel of the thin film transistor formed on the scanning line region. The slit is used as a mask and a pattern of a channel protection film for determining the channel of the thin film transistor is formed by exposure form a back surface of a substrate. According to this method, a desirable channel length can be obtained, and the scanning line region, facing to the channel through the slit, functions as an auxiliary region, so that the resistance of the scanning line region can be reduced.

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Yokohama, Japan

Tomoko Kitazawa