Nec Electronics Corporation

Paramount Bed Company, Limited

Renesas Electronics Corporation

Tomoko Inoue

Ken Inoue

Takamasa Kogure

Yasuaki Tsuchiya

Toshihide Shiino

Takashi Tonegawa

A posture determination apparatus including at least two vibration sensors and a controller. The controller causes the vibration sensors to detect vibrations while the user is lying in bed, calculates waveforms from the detected vibrations and recognizes the characteristics of the waveforms, and determines the posture of the user based on the characteristics. Thereby, it is possible to provide a posture determination apparatus and capable of appropriately determining the posture of the user which is one factor of the state of the user.

Posture determination apparatus

An evaluating apparatus of this application includes a detector configured to detect a biological signal of a user, and a controller configured to calculate an amount of activity of the user from the biological signal, determine whether the user is sleeping during a first period by comparing the amount of activity with a low threshold, and determine whether the user is sleeping during a second period after the first period by comparing the amount of activity with a high threshold, the low threshold being lower than the high threshold.

Evaluating apparatus and non-transitory computer readable medium storing program

A biological signal of a subject is acquired so as to calculate biological information from the acquired biological signal. When the biological information has been determined to be anomaly, whether the biological information is one that was calculated under a high-accuracy condition is determined. When the biological information is determined to be one that was calculated under the high-accuracy condition, a notice is given based on a first criterion. In the other cases, a notice is given based on a second criterion. Thereby, it is possible to provide an abnormality notification system that can give a necessary notification appropriately while suppressing unnecessary notification, by changing the criteria for notification in accordance with the accuracy of the determined biological information when the biological information of the subject was determined to be anomaly.

Abnormality notification system, abnormality notification method, and program

A posture determination apparatus including at least two vibration sensors and a controller. The controller causes the vibration sensors to detect vibrations while the user is lying in bed, calculates waveforms from the detected vibrations and recognizes the characteristics of the waveforms, and determines the posture of the user based on the characteristics. Thereby, it is possible to provide a posture determination apparatus capable of appropriately determining the posture of the user which is one factor of the state of the user.

A semiconductor device includes a silicon substrate, a capacitor element having a lower electrode, a capacitor dielectric film, a TiN film, and a W film, and an interlayer insulation film covering the end and a portion of the upper surface of the lower electrode and disposed with a concave portion at a position corresponding to the lower electrode. The lower electrode is disposed selectively at the bottom of the concave portion, the upper surface of the lower electrode is exposed from the interlayer insulation film in the region for forming the concave portion, the side wall for the concave portion of the interlayer insulation film situates to the inner side of the lower electrode from the end of the lower electrode, and the capacitor dielectric film is disposed so as to cover the upper surface of the lower electrode and cover the interlayer insulation from the side wall for the concave portion to the upper surface of the interlayer insulation film.

Semiconductor device having capacitor formed on plug, and method of forming the same

Provided is a semiconductor device which includes a capacitor element having a flat-plate-type lower electrode provided over a semiconductor substrate, a flat-plate-type TiN film provided over the lower electrode in parallel therewith, and a capacitor film provided between the lower electrode and the TiN film; and a first Cu plug brought into contact with the bottom surface of the lower electrode, and is composed of a metal material, wherein the capacitor film has a film which contains an organic molecule as a constituent.

Semiconductor device having capacitor element

The present invention provides a semiconductor device comprising: a semiconductor substrate having a DRAM portion and a Logic portion; a first transistor in said DRAM portion; a second transistor in said Logic portion; a first insulating layer covering said DRAM portion and said Logic portion; a first contact plug formed in said first insulating layer in electrically contact with said first transistor in said DRAM portion; a first bit line for said DRAM portion formed on said first insulating layer in electrically contact with said first contact plug; a nitride film formed in contact with said first insulating layer to cover said DRAM portion and said Logic portion, wherein said first bit line locating between said first insulating layer and said nitride film.

Semiconductor device with DRAM portion having capacitor-over-bit-line structure and logic portion

The present invention provides a method of increasing designing freedom of a position to form a capacitor, and increasing a capacitance value thereof. When forming a first contact, a tungsten plug for increasing a surface area of a lower electrode is formed in a contact interlayer film at a region where the capacitor is to be formed. Since the tungsten plug does not have to be formed right above the capacitor contact, a position to form the capacitor is not limited by a position where the capacitor contact is provided.

Semiconductor device and method of manufacturing the same

A circuit provides an inhibition to the short circuit between the bit line and the capacitance contact, without employing a self alignment contact (SAC) process. A hard mask is formed on the bit line upper surface and a side wall formed on the side surface of the bit line by etching back a nitride film. A bit contact interlayer film without the SAC structure is etched off except where bit line is formed. A direct nitride film is formed on the entire top and side surface of the bit line so as to cover the bit line in one processing step. Since the upper and side nitride film thicknesses are substantially the same, the height of the bit line can be reduced, enabling further miniaturization. In addition, since the sidewall nitride film is formed without an etch back process, it can more easily be formed with a constant film thickness.

Semiconductor device memory cell

The short circuit between the bit line and thee cell contact can be prevented without considerably increasing the number of the manufacturing processes. The bit lineelectrically coupled to the cell contactis formed of the material, which is same as the material of cell contact. In the process for forming the bit lineon the cell contact interlayer filmby etching, the etching for creating an upper surface of the cell contactthat is not coupled to the bit linebeing lower than an upper surface of the cell contactthat is coupled to the bit line. Further, after the formation of the bit line, the barrier metal layerformed on the lower surface of the bit lineis selectively etched.

Semiconductor device having plural electroconductive plugs

The present invention provides an inhibition to the short circuit between the bit line and the capacitance contact, without employing a self alignment contact (SAC) process, in which a hard mask is formed on the upper surface of the bit line and a side wall formed on the side surface of the bit line by etching back a nitride film. A bit contact interlayer film of the conventional semiconductor device which does not have the SAC structure is etched off except the portion where bit line is formed, and then direct nitride film is formed on the entire surface of the top surface and the side surface of the bit line so as to cover the bit line in a same processing step. Since the film thickness of the nitride film disposed on the upper surface of the bit line is designed to be substantially the same as that disposed on the side surface of the nitride film, the height of the bit line itself can be reduced, and thus a further miniaturization becomes possible. In addition, since the nitride film is formed on the side wall of the bit line without requiring an etch back process according to the process of the present invention, the nitride film having a constant film thickness can be easily formed on the side wall of the bit line, as compared with the conventional SAC structure.

In a method of forming a metal wiring line, a first insulating film is formed directly or indirectly on a semiconductor substrate. A second insulating film is formed on the first insulating film. A wiring line groove is formed to pass through the second insulating film to an inside of the first insulating film. A conductive film is formed to fill the wiring line groove and to cover the second insulating film. The conductive film and the second insulating film are removed by a first CMP polishing process, using the first insulating film as a stopper film, until the first insulating film is exposed.

Method of forming metal wiring line including using a first insulating film as a stopper film

A method of manufacturing a semiconductor device includes the steps of forming a sunken section in an insulating film formed on a substrate and forming a barrier metal film on the insulating film inclusive of the sunken section. The method also includes forming a copper-based film over the entire surface so as to fill up the sunken section and forming a copper-based metal interconnection. The interconnection is formed by polishing this substrate surface by the chemical mechanical polishing method, using a polishing slurry containing a silica polishing material, an oxidizing agent, an amino acid, a triazole-based compound and water. A content ratio of the amino acid to the triazole-based compound (amino acid/triazole-based compound (weight ratio)) is 5 to 8.

Growing community of inventors

Kanagawa, Japan

Tomoko Inoue