Mitsubishi Denki Kabushiki Kaisha

Canon Anelva Corporation

Tomoki Oku

Ryo Hattori

Shinichi Miyakuni

Yasutaka Kohno

Toshihiko Shiga

Masahiro Totsuka

Nobuyuki Kasai

Hirofumi Nakano

Teruyuki Shimura

Takahide Ishikawa

Masayuki Sakai

Naohito Yoshida

Yasushi Kamiya

Shuji Nomura

Yasutaka Kohno, Deceased

Masahiro Totuka

Hitoshi Morisaki

The silicon nitride film forming method deposits a silicon nitride film on the substrate surface by maintaining the heating element at a predetermined temperature and by decomposing and/or activating a raw material gas supplied from the gas supply system.

Silicon nitride film forming method

A method of manufacturing a semiconductor device including a gallium nitride related semiconductor. The method include preparing a substrate having surface of a gallium nitride related semiconductor; contacting the surface with atomic nitrogen, which is obtained by decomposing a nitrogen-containing gas in a catalytic reaction, to nitride the surface; and forming, on the surface, a gate electrode and source and drain electrodes opposing each other across the gate electrode.

Method of manufacturing semiconductor device

A process of manufacturing a semiconductor device uses catalytic chemical vapor deposition. In the process, a reaction chamber containing a catalyzer and a substrate has gasses, including silane, ammonia, and hydrogen supplied to the reaction chamber. The gases are brought into contact with the catalyzer and then with the substrate to deposit a silicon nitride film.

Process for manufacturing a semiconductor device

A semiconductor device includes a self-aligned refractory metal constituent in a recess in a semiconductor substrate and having the same plane pattern as a bottom surface of the recess. The width of the constituent is determined by the plane pattern of the recess and, accordingly, the pattern width of the constituent is easily controlled by the plane pattern of the recess.

Semiconductor device with refractory metal element

A method of making a semiconductor device includes forming a recess in a compound semiconductor substrate using a patterned insulating film on a surface of the substrate, implanting dopant ions at the bottom of the recess to form a channel region, and depositing a refractory metal film. The refractory metal film is etched, using a resist pattern, to form a gate electrode and additional dopant ions are implanted to form relatively highly doped regions intersecting the channel region. Very highly doped regions are formed my implantation, after removing the insulating film, using the gate electrode and remainder of the resist mask as an implantation mask. After stripping the resist, annealing to activate the implanted ions, and depositing a passivating film on the substrate and gate electrode, source and drain electrodes are formed. The field effect transistor thus produced has a high breakdown voltage, improved reliability, a highly controlled pinch-off voltage, and improved transconductance and operating speed.

Method of fabricating semiconductor device

An MIM capacitor includes a lower electrode; a first insulating film disposed on the lower electrode; a second insulating film disposed on the first insulating film and having a first opening exposing a portion of the surface of the first insulating film on the lower electrode, the first opening having a perimeter; a third insulating film disposed on the second insulating film and having a second opening exposing a portion of the surface of the second insulating film, the second opening having a perimeter that surrounds the perimeter of the first opening on the second insulating film; and an upper electrode disposed on the first insulating film through the first opening and extending onto the second insulating film.

Capacitor

A semiconductor device includes a semiconductor substrate; a first active layer disposed on the semiconductor substrate; a second active layer disposed on the first active layer; a first electrode including a lower stage disposed on the second active layer and an upper stage disposed on the lower stage and having an overhanging portion protruding from the lower stage; an insulating film continuously covering a surface of the second active layer, a side surface of the lower stage of the first electrode, and a lower surface and a side surface of the overhanging portion of the upper stage; and a second electrode disposed on the surface of the first active layer at opposite sides of the second active layer, self-aligned with the second active layer. The distance between the second electrode and the second active layer is minimized and the thickness of the second electrode can be about 7000 .ANG., minimizing the resistance of the first active layer and improving high frequency characteristics. Electrical separation between the first and second active layers can be achieved reliably. Recombination at the surface of the second active layer is suppressed.

Compound semiconductor bipolar transistor

A semiconductor device includes a compound semiconductor body having a recess, the recess having a bottom and a hollow, and a refractory metal gate electrode having a lower portion within the hollow. The compound semiconductor body includes a compound semiconductor substrate; a channel layer including a compound semiconductor of a first conductivity type, the channel layer being located on the substrate between the gate electrode and the substrate; first active layers of the compound semiconductor and of the first conductivity type located on regions of the substrate in the recess where the channel layer is not present; and second active layers of the compound semiconductor and of the first conductivity type located on regions of the substrate in the recess where the channel layer is not present; and second active layers of the compound semiconductor of the first conductivity type located on regions of the substrate sandwiching the recess. Therefore, the controllable region in the channel layer is not adversely affected by a depletion layer produced at the interface between the first active layers and a passivation film, whereby an unwanted reduction in the control speed in the channel layer due to the charging and discharging of carriers in traps at the interface is avoided.

Recessed gate field effect transistor

A method of producing a field effect transistor that includes forming a step in a compound semiconductor substrate, forming a first insulating side wall at the step, forming an etch blocking layer on the substrate, removing the first insulating side wall, and etching the substrate not protected by the etch blocking layer to produce a recess. Subsequently, a second insulating side wall is formed at the sides of the recess, a refractory metal and a low resistance metal are sequentially deposited and formed as a gate electrode, and finally, source and drain electrodes are formed.

Method of making a narrow gate electrode for a field effect transistor

A method for manufacturing a semiconductor device including forming an electrode on a part of a semiconductor substrate, depositing an insulating film on the semiconductor substrate and on the electrode, and forming a contact hole penetrating through the insulating film to expose a part of the electrode; forming a barrier metal layer on the electrode in the contact hole, on the internal side surface of the contact hole, and on the surface of the insulating film; and depositing a metal layer on the barrier metal layer and patterning the metal layer and the barrier metal layer to form a wiring layer wherein the barrier metal layer comprises a metal that does not form an intermetallic material by solid state diffusion with either of the electrode and the metal layer even at elevated temperatures.

A method for producing a T-shaped gate electrode of a semiconductor device including forming an insulating film on a semiconductor substrate, etching away a prescribed portion of the insulating film, depositing a metal film having a prescribed thickness, forming a first photoresist film and removing the photoresist film except where the insulating film has been removed, forming a second photoresist film, patterning the second photoresist film to expose the metal film along a side wall of the insulating film, etching away a portion of the metal film using the first and second photoresist films as a mask, depositing a gate metal and removing the first and second photoresist films and overlying gate metal by lift-off, and etching away the metal films remaining on the semiconductor substrate and the insulating film. Thereby, a T-shaped gate electrode with shortened length is formed.

FET with a T-shaped gate of a particular structure

A particle beam irradiates a thermohardening resin and selectively hardens the thermohardening resin of the implanted region. The non-hardened resin not irradiated is removed with high selectivity and an inverted pattern of the hardened resin remains as a mask. Using the same photoresist mask employed in the irradiation for selective hardening, ion implantation through the hardened resin forms spaced apart implanted regions in the substrate. The removal of the photoresist and the non-hardened resin leaves an aperture for metal deposition to form Schottky barrier. Hardened resin from portions of spaced apart implanted regions is removed, followed by metal deposition forming source and drain electrodes to complete a MESFET. Spin-on-glass as the thermohardening resin is also disclosed.

Production method of a MESFET semiconductor device

A method for producing a Schottky barrier gate type field effect transistor includes producing a low concentration active region at a desired position of a semi-insulating compound semiconductor substrate and producing a gate electrode comprising refractory metal on the active region, producing a first insulating film and etching the same thereby to produce first side wall assist films comprising the first insulating film at both side walls of the gate electrode, removing one of the first side wall assist films at the side where a source electrode is to be produced, depositing a second insulating film to the thickness less than that of the first insulating film, etching the second insulating film thereby to produce a second side wall assist film having narrower width than that of the first side wall assist film at the side wall of the gate electrode where the source electrode is to be produced, and conducting ion implantation using the first and second side wall assist films and the gate electrode as a mask thereby to produce high concentration active regions in asymmetrical configurations at sides of the gate electrode.

Semiconductor device

A method of producing a field effect transistor includes depositing a first insulating film and a refractory metal on a semiconductor substrate, forming a first aperture penetrating the first insulating film and the refractory metal film to provide a gate electrode production region, depositing a second insulating film on the refractory metal film, etching the second insulating film in a direction perpendicular to the surface of the substrate leaving portions of the second insulating film on opposite side walls of the first aperture to form a second aperture, defining a gate length, depositing a gate metal, and patterning the gate metal layer, the first insulating film, and the refractory metal film in a prescribed width to form a T-shaped gate structure. During etching the second insulating film, since the refractory metal film serves as a etch stopping layer, the first insulating film is not etched and its thickness remains as deposited. Therefore, the space between the over-hanging portion of the T-shaped gate electrode and the source electrode increases and the gate-to-source capacitance is reduced.

Method of manufacturing a field effect transistor with a T-shaped gate

A particle beam irradiates a thermohardening resin and selectively hardens the thermohardening resin of the implanted region. The non-hardened resin not irradiated is removed with high selectivity and an inverted pattern of the hardened resin remains as a mask. In one embodiment, a gate electrode is produced in an aperture pattern produced by transfer of the inverted pattern and source and drain electrodes are provided at other aperture patterns to form an HEMT having a narrow gate self-aligned with the source and drain electrodes.

Growing community of inventors

Itami, Japan

Tomoki Oku